Patents by Inventor Matthew M. Reiss

Matthew M. Reiss has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Stress reduction in flip-chip PBGA packaging by utilizing segmented chips and/or chip carriers
    Patent number: 6989607
    Abstract: A method and structure to electrically couple a semiconductor device to a substrate that is divided into a plurality of segments. Alternatively, a semiconductor device may be divided into a plurality of segments and the plurality of segments are electrically coupled to a single substrate.
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: January 24, 2006
    Assignee: International Business Machines Corporation
    Inventors: Krishna Darbha, Miguel A. Jimarez, Matthew M. Reiss, Sanjeev B. Sathe, Charles G. Woychik
  • Stress reduction in flip-chip PBGA packaging by utilizing segmented chips and/or chip carriers
    Publication number: 20040021205
    Abstract: A method and structure to electrically couple a semiconductor device to a substrate that is divided into a plurality of segments. Alternatively, a semiconductor device may be divided into a plurality of segments and the plurality of segments are electrically coupled to a single substrate.
    Type: Application
    Filed: July 29, 2003
    Publication date: February 5, 2004
    Inventors: Krishna Darbha, Miguel A. Jimarez, Matthew M. Reiss, Sanjeev B. Sathe, Charles G. Woychik
  • Method of forming an apparatus to reduce thermal fatigue stress on flip chip solder connections
    Patent number: 6667557
    Abstract: A method for providing a package for a semiconductor chip that minimizes stresses and strains that arise from differential thermal expansion on chip-to-substrate or chip-to-card interconnections. A collar element of one or more elements is provided. Adhesive material connects the collar element to the electric device and to the substrate that supports it, forming a unitary electrical package.
    Type: Grant
    Filed: April 9, 2003
    Date of Patent: December 23, 2003
    Assignee: International Business Machines Corporation
    Inventors: David J. Alcoe, Eric A. Johnson, Matthew M. Reiss, Charles G. Woychik
  • METHOD OF FORMING AN APPARATUS TO REDUCE THERMAL FATIGUE STRESS ON FLIP CHIP SOLDER CONNECTIONS
    Publication number: 20030210531
    Abstract: The present invention provides a package for a semiconductor chip that minimizes stresses and strains that arise from differential thermal expansion on chip-to-substrate or chip-to-card interconnections. A collar element of one or more elements is provided. Adhesive material connects the collar element to the electric device and to the substrate that supports it, forming a unitary electrical package.
    Type: Application
    Filed: April 9, 2003
    Publication date: November 13, 2003
    Inventors: David J. Alcoe, Eric A. Johnson, Matthew M. Reiss, Charles G. Woychik
  • Stress reduction in flip-chip PBGA packaging by utilizing segmented chip carries
    Patent number: 6639302
    Abstract: A method and structure to electrically couple a semiconductor device to a substrate that is divided into a plurality of segments. Alternatively, a semiconductor device may be divided into a plurality of segments and the plurality of segments are electrically coupled to a single substrate.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: October 28, 2003
    Assignee: International Business Machines Corporation
    Inventors: Krishna Darbha, Miguel A. Jimarez, Matthew M. Reiss, Sanjeev B. Sathe, Charles G. Woychik
  • STRESS REDUCTION IN FLIP-CHIP PBGA PACKAGING BY UTILIZING SEGMENTED CHIP CARRIERS
    Publication number: 20030178649
    Abstract: A method and structure to electrically couple a semiconductor device to a substrate that is divided into a plurality of segments. Alternatively, a semiconductor device may be divided into a plurality of segments and the plurality of segments are electrically coupled to a single substrate.
    Type: Application
    Filed: March 20, 2002
    Publication date: September 25, 2003
    Applicant: International Business Machines Corporation
    Inventors: Krishna Darbha, Miguel A. Jimarez, Matthew M. Reiss, Sanjeev B. Sathe, Charles G. Woychik
  • Apparatus to reduce thermal fatigue stress on flip chip solder connections
    Patent number: 6570259
    Abstract: The present invention provides a package for a semiconductor chip that minimizes stresses and strains that arise from differential thermal expansion on chip-to-substrate or chip-to-card interconnections. A collar element of one or more elements is provided. Adhesive material connects the collar element to the electric device and to the substrate that supports it, forming a unitary electrical package.
    Type: Grant
    Filed: March 22, 2001
    Date of Patent: May 27, 2003
    Assignee: International Business Machines Corporation
    Inventors: David J. Alcoe, Eric A. Johnson, Matthew M. Reiss, Charles G. Woychik
  • Apparatus to reduce thermal fatigue stress on flip chip solder connections
    Publication number: 20020135063
    Abstract: The present invention provides a package for a semiconductor chip that minimizes stresses and strains that arise from differential thermal expansion on chip-to-substrate or chip-to-card interconnections. A collar element of one or more elements is provided. Adhesive material connects the collar element to the electric device and to the substrate that supports it, forming a unitary electrical package.
    Type: Application
    Filed: March 22, 2001
    Publication date: September 26, 2002
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David J. Alcoe, Eric A. Johnson, Matthew M. Reiss, Charles G. Woychik