Patents by Inventor Matthew Michael Nowak
Matthew Michael Nowak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9298946Abstract: One feature pertains to a method of implementing a physically unclonable function that includes providing an array of metal-insulator-metal (MIM) devices, where the MIM devices are configured to represent a first resistance state or a second resistance state and a plurality of the MIM devices are initially at the first resistance state. The MIM devices have a random breakdown voltage that is greater than a first voltage and less than a second voltage, where the breakdown voltage represents a voltage that causes the MIM devices to transition from the first resistance state to the second resistance state. The method further includes applying a signal line voltage to the MIM devices to cause a portion of the MIM devices to randomly breakdown and transition from the first resistance state to the second resistance state, the signal line voltage greater than the first voltage and less than the second voltage.Type: GrantFiled: November 5, 2013Date of Patent: March 29, 2016Assignee: QUALCOMM IncorporatedInventors: Xiaochun Zhu, Steven M. Millendorf, Xu Guo, David M. Jacobson, Kangho Lee, Seung H. Kang, Matthew Michael Nowak
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Publication number: 20160071847Abstract: A method for half-node scaling a circuit layout in accordance with an aspect of the present disclosure includes vertical devices on a die. The method includes reducing a fin pitch and a gate pitch of the vertical devices on the die. The method also includes scaling a wavelength to define at least one reduced area geometric pattern of the circuit layout.Type: ApplicationFiled: September 8, 2014Publication date: March 10, 2016Inventors: Stanley Seungchul SONG, Kern RIM, Jeffrey Junhao XU, Matthew Michael NOWAK, Choh Fei YEAP, Roawen CHEN
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Patent number: 9268720Abstract: A load balancing in a multiple DRAM system comprises interleaving memory data across two or more memory channels. Access to the memory channels is controlled by memory controllers. Bus masters are coupled to the memory controllers via an interconnect system and memory requests are transmitted from the bus masters to the memory controller. If congestion is detected in a memory channel, congestion signals are generated and transmitted to the bus masters. Memory requests are accordingly withdrawn or rerouted to less congested memory channels based on the congestion signals.Type: GrantFiled: August 31, 2010Date of Patent: February 23, 2016Assignee: QUALCOMM IncorporatedInventors: Feng Wang, Shiqun Gu, Jonghae Kim, Matthew Michael Nowak
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Patent number: 9264013Abstract: Systems for reducing magnetic coupling in integrated circuits (ICs) are disclosed. Related components and methods are also disclosed. The ICs have a plurality of inductors. Each inductor generates a magnetic flux that has a discernible axis. To reduce magnetic coupling between the inductors, the flux axes are designed so as to be non-parallel. In particular, by making the flux axes of the inductors non-parallel to one another, magnetic coupling between the inductors is reduced relative to the situation where the flux axes are parallel. This arrangement may be particularly well suited for use in diplexers having a low pass and a high pass filter.Type: GrantFiled: September 6, 2013Date of Patent: February 16, 2016Assignee: QUALCOMM IncorporatedInventors: Chengjie Zuo, Jonghae Kim, Daeik Daniel Kim, Mario Francisco Velez, Changhan Hobie Yun, Je-Hsiung Jeffrey Lan, Robert Paul Mikulka, Matthew Michael Nowak
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Publication number: 20160013133Abstract: Systems and methods are directed to a semiconductor device, which includes an integrated circuit, wherein the integrated circuit includes at least a first layer comprising two or more Tungsten lines and at least one air gap between at least two Tungsten lines, the air gaps to reduce capacitance. An interposer is coupled to the integrated circuit, to reduce stress on the two or more Tungsten lines and the at least one air gap. A laminated package substrate may be attached to the interposer such that the interposer is configured to absorb mechanical stress induced by mismatch in coefficient of thermal expansion (CTE) between the laminated package substrate and the interposer and protect the air gap from the mechanical stress.Type: ApplicationFiled: July 14, 2014Publication date: January 14, 2016Inventors: Shiqun GU, Matthew Michael NOWAK, Jeffrey Junhao XU
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Publication number: 20160012896Abstract: An apparatus includes a multiple time programmable (MTP) memory device. The MTP memory device includes a metal gate, a substrate material, and an oxide structure between the metal gate and the substrate material. The oxide structure includes a hafnium oxide layer and a silicon dioxide layer. The hafnium oxide layer is in contact with the metal gate and in contact with the silicon dioxide layer. The silicon dioxide layer is in contact with the substrate material. The MTP device includes a transistor, and a non-volatile state of the MTP memory device is based on a threshold voltage of the transistor.Type: ApplicationFiled: January 21, 2015Publication date: January 14, 2016Inventors: Xia Li, Jeffrey Junhao Xu, Xiao Lu, Matthew Michael Nowak, Seung Hyuk Kang, Xiaonan Chen, Zhongze Wang, Yu Lu
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Patent number: 9230630Abstract: One feature pertains to a method for implementing a physically unclonable function (PUF). The method includes providing an array of magnetoresistive random access memory (MRAM) cells, where the MRAM cells are each configured to represent one of a first logical state and a second logical state. The array of MRAM cells are un-annealed and free from exposure to an external magnetic field oriented in a direction configured to initialize the MRAM cells to a single logical state of the first and second logical states. Consequently, each MRAM cell has a random initial logical state of the first and second logical states. The method further includes sending a challenge to the MRAM cell array that reads logical states of select MRAM cells of the array, and obtaining a response to the challenge from the MRAM cell array that includes the logical states of the selected MRAM cells of the array.Type: GrantFiled: November 5, 2013Date of Patent: January 5, 2016Assignee: QUALCOMM IncorporatedInventors: Xiaochun Zhu, Steven M. Millendorf, Xu Guo, David M. Jacobson, Kangho Lee, Seung H. Kang, Matthew Michael Nowak
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Patent number: 9214214Abstract: One feature pertains to a method of implementing a physically unclonable function (PUF). The method includes exposing an array of magnetoresistive random access memory (MRAM) cells to an orthogonal external magnetic field. The MRAM cells are each configured to represent one of a first logical state and a second logical state, and the orthogonal external magnetic field is oriented in an orthogonal direction to an easy axis of a free layer of the MRAM cells to place the MRAM cells in a neutral logical state that is not the first logical state or the second logical state. The method further includes removing the orthogonal external magnetic field to place each of the MRAM cells of the array randomly in either the first logical state or the second logical state.Type: GrantFiled: November 5, 2013Date of Patent: December 15, 2015Assignee: QUALCOMM IncorporatedInventors: Xiaochun Zhu, Steven M. Millendorf, Xu Guo, David M. Jacobson, Kangho Lee, Seung H. Kang, Matthew Michael Nowak
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Patent number: 9202789Abstract: Some novel features pertain to an integrated device package (e.g., die package) that includes a package substrate, a die, an encapsulation layer and a first set of metal layers. The package substrate includes a first surface and a second surface. The die is coupled to the first surface of the package substrate. The encapsulation layer encapsulates the die. The first set of metal layers is coupled to a first exterior surface of the encapsulation layer. In some implementations, the first set of metal layers is configured to operate as a die-to-wire connector of the integrated device package. In some implementations, the integrated device package includes a second set of metal layers coupled to the second surface of the package substrate. In some implementations, the integrated device package includes a second set of metal layers coupled to a second exterior surface of the encapsulation layer.Type: GrantFiled: April 16, 2014Date of Patent: December 1, 2015Assignee: QUALCOMM IncorporatedInventors: Daeik Daniel Kim, Mario Francisco Velez, Jonghae Kim, Matthew Michael Nowak, Chengjie Zuo, Changhan Hobie Yun, David Francis Berdy, Robert Paul Mikulka
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Patent number: 9202705Abstract: An integrated circuit (IC) module with a lead frame micro-needle for a medical device, and methods of forming the IC module are described. The methods include forming a lead frame blank including a micro-needle integrally formed therein. The micro-needle may be bent beyond an initial lower side of the lead frame blank. The initial lower side may be joined with a protection layer such that the bent micro-needle is embedded in the protection layer, which may be removably attached to the initial lower side and the bent micro-needle. An IC component may be affixed to an upper side of the lead frame blank. The IC component and an upper surface of a core of the lead frame blank may be encapsulated with a molding compound forming a packaging of the IC module. Removal of the protection layer may expose the bent micro-needle projecting away from the packaging.Type: GrantFiled: August 12, 2015Date of Patent: December 1, 2015Assignee: QUALCOMM IncorporatedInventors: Kenneth Kaskoun, Rongtian Zhang, Matthew Michael Nowak, Shiqun Gu
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Publication number: 20150304059Abstract: An apparatus is disclosed that includes a frequency multiplexer circuit coupled to an input node and configured to receive an input signal via the input node. The frequency multiplexer circuit comprises a first filter circuit, a second filter circuit, and a third filter circuit. The apparatus also includes a switching circuit that is configurable to couple at least two of a first output of the first filter circuit, a second output of the second filter circuit, or a third output of the third filter circuit to a single output port.Type: ApplicationFiled: April 8, 2015Publication date: October 22, 2015Inventors: Chengjie Zuo, Daeik Daniel Kim, David Francis Berdy, Changhan Hobie Yun, Je-Hsiung Jeffrey Lan, Robert Paul Mikulka, Mario Francisco Velez, Jonghae Kim, Matthew Michael Nowak, Ryan Scott C. Spring, Xiangdong Zhang
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Publication number: 20150303148Abstract: Some novel features pertain to an integrated device package (e.g., die package) that includes a package substrate, a die, an encapsulation layer and a first set of metal layers. The package substrate includes a first surface and a second surface. The die is coupled to the first surface of the package substrate. The encapsulation layer encapsulates the die. The first set of metal layers is coupled to a first exterior surface of the encapsulation layer. In some implementations, the first set of metal layers is configured to operate as a die-to-wire connector of the integrated device package. In some implementations, the integrated device package includes a second set of metal layers coupled to the second surface of the package substrate. In some implementations, the integrated device package includes a second set of metal layers coupled to a second exterior surface of the encapsulation layer.Type: ApplicationFiled: April 16, 2014Publication date: October 22, 2015Applicant: QUALCOMM IncorporatedInventors: Daeik Daniel Kim, Mario Francisco Velez, Jonghae Kim, Matthew Michael Nowak, Chengjie Zuo, Changhan Hobie Yun, David Francis Berdy, Robert Paul Mikulka
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Patent number: 9138191Abstract: An integrated circuit (IC) module with a lead frame micro-needle for a medical device, and methods of forming the IC module are described. The methods include forming a lead frame blank including a micro-needle integrally formed therein. The micro-needle may be bent beyond an initial lower side of the lead frame blank. The initial lower side may be joined with a protection layer such that the bent micro-needle is embedded in the protection layer, which may be removably attached to the initial lower side and the bent micro-needle. An IC component may be affixed to an upper side of the lead frame blank. The IC component and an upper surface of a core of the lead frame blank may be encapsulated with a molding compound forming a packaging of the IC module. Removal of the protection layer may expose the bent micro-needle projecting away from the packaging.Type: GrantFiled: July 9, 2014Date of Patent: September 22, 2015Assignee: QUALCOMM IncorporatedInventors: Kenneth Kaskoun, Rongtian Zhang, Matthew Michael Nowak, Shiqun Gu
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Patent number: 9135976Abstract: A probabilistic programming current is injected into a cluster of bi-stable probabilistic switching elements, the probabilistic programming current having parameters set to result in a less than unity probability of any given bi-stable switching element switching, and a resistance of the cluster of bi-stable switching elements is detected. The probabilistic programming current is injected and the resistance of the cluster state detected until a termination condition is met. Optionally the termination condition is detecting the resistance of the cluster of bi-stable switching elements at a value representing a multi-bit data.Type: GrantFiled: December 12, 2013Date of Patent: September 15, 2015Assignee: QUALCOMM IncorporatedInventors: Wenqing Wu, Kendrick Hoy Leong Yuen, Xiaochun Zhu, Seung Hyuk Kang, Matthew Michael Nowak, Jeffrey Alexander Levin, Robert P. Gilmore, Nicholas Ka Ming Yu
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Publication number: 20150201495Abstract: An integrated circuit device includes a first substrate supporting a pair of conductive interconnects, for example pillars. The device also includes a second substrate on the pair of conductive interconnects. The pair of conductive interconnects is arranged to operate as a first 3D solenoid inductor. The device further includes a conductive trace coupling the pair of conductive interconnects to each other.Type: ApplicationFiled: January 14, 2014Publication date: July 16, 2015Applicant: QUALCOMM IncorporatedInventors: Daeik Daniel KIM, Mario Francisco VELEZ, Chengjie ZUO, Changhan Hobie YUN, Jonghae KIM, Matthew Michael NOWAK
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Publication number: 20150092314Abstract: A system includes a first connector coupled to a first surface of a substrate. The first connector enables the system to be electrically coupled to a first device external to the substrate. The system includes a second connector coupled to a second surface of the substrate. The system also includes a plurality of conductive vias extending through the substrate from the first surface to the second surface. The plurality of conductive vias surrounds the first connector and the second connector. The plurality of conductive vias is electrically coupled together to form a toroidal inductor. A first lead of the toroidal inductor is electrically coupled to the first connector. A second lead of the toroidal inductor is electrically coupled to the second connector.Type: ApplicationFiled: September 27, 2013Publication date: April 2, 2015Applicant: QUALCOMM IncorporatedInventors: Daeik Daniel Kim, Young Kyu Song, Mario Francisco Velez, Jonghae Kim, Changhan Hobie Yun, Chengjie Zuo, Xiaonan Zhang, Ryan David Lane, Matthew Michael Nowak
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Patent number: 8987062Abstract: Thermal conductivity in a stacked IC device can be improved by constructing one or more active temperature control devices within the stacked IC device. In one embodiment, the control devices are thermal electric (TE) devices, such as Peltier devices. The TE devices can then be selectively controlled to remove or add heat, as necessary, to maintain the stacked IC device within a defined temperature range. The active temperature control elements can be P-N junctions created in the stacked IC device and can serve to move the heat laterally and/or vertically, as desired.Type: GrantFiled: October 17, 2013Date of Patent: March 24, 2015Assignee: QUALCOMM IncorporatedInventors: Shiqun Gu, Matthew Michael Nowak, Thomas Robert Toms
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Publication number: 20150071431Abstract: One feature pertains to a method of implementing a physically unclonable function (PUF). The method includes exposing an array of magnetoresistive random access memory (MRAM) cells to an orthogonal external magnetic field. The MRAM cells are each configured to represent one of a first logical state and a second logical state, and the orthogonal external magnetic field is oriented in an orthogonal direction to an easy axis of a free layer of the MRAM cells to place the MRAM cells in a neutral logical state that is not the first logical state or the second logical state. The method further includes removing the orthogonal external magnetic field to place each of the MRAM cells of the array randomly in either the first logical state or the second logical state.Type: ApplicationFiled: November 5, 2013Publication date: March 12, 2015Applicant: QUALCOMM IncorporatedInventors: Xiaochun Zhu, Steven M. Millendorf, Xu Guo, David M. Jacobson, Kangho Lee, Seung H. Kang, Matthew Michael Nowak
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PHYSICALLY UNCLONABLE FUNCTION BASED ON PROGRAMMING VOLTAGE OF MAGNETORESISTIVE RANDOM-ACCESS MEMORY
Publication number: 20150070979Abstract: One feature pertains to a method of implementing a physically unclonable function. The method includes initializing an array of magnetoresistive random-access memory (MRAM) cells to a first logical state, where each of the MRAM cells have a random transition voltage that is greater than a first voltage and less than a second voltage. The transition voltage represents a voltage level that causes the MRAM cells to transition from the first logical state to a second logical state. The method further includes applying a programming signal voltage to each of the MRAM cells of the array to cause at least a portion of the MRAM cells of the array to randomly change state from the first logical state to the second logical state, where the programming signal voltage is greater than the first voltage and less than the second voltage.Type: ApplicationFiled: November 5, 2013Publication date: March 12, 2015Applicant: QUALCOMM IncorporatedInventors: Xiaochun Zhu, Steven M. Millendorf, Xu Guo, David M. Jacobson, Kangho Lee, Seung H. Kang, Matthew Michael Nowak -
Publication number: 20150071432Abstract: One feature pertains to least one physically unclonable function based on an array of magnetoresistive random-access memory (MRAM) cells. A challenge to the array of MRAM cells may identify some of the cells to be used for the physically unclonable function. Each MRAM cell may include a plurality of magnetic tunnel junctions (MTJs), where the MTJs may exhibit distinct resistances due to manufacturing or fabrication variations. A response to the challenge may be obtained for each cell by using the resistance(s) of one or both of the MTJs for a cell to obtain a value that serves as the response for that cell. The responses for a plurality of cells may be at least partially mapped to provide a unique identifier for the array. The responses generated from the array of cells may serve as a physically unclonable function that may be used to uniquely identify an electronic device.Type: ApplicationFiled: November 11, 2013Publication date: March 12, 2015Applicant: QUALCOMM IncorporatedInventors: Xiaochun Zhu, Steven M. Millendorf, Xu Guo, David Merrill Jacobson, Kangho Lee, Seung H. Kang, Matthew Michael Nowak