Patents by Inventor Matthew Monroe

Matthew Monroe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11963691
    Abstract: A surgical instrument, has an end effector that includes an ultrasonic blade, and a clamp arm that moves relative to the ultrasonic blade from an opened position toward an intermediate position and a closed position. The clamp arm is offset from the ultrasonic blade to define a predetermined gap in the intermediate position between the opened position and the closed position. A clamp arm actuator connects to the clamp arm and moves from an opened configuration to a closed configuration to direct the clamp arm from the opened position toward the intermediate position and the closed position. A spacer connects with the clamp arm to inhibit movement of the clamp arm from the intermediate position toward the closed position for maintaining the predetermined gap between the clamp arm and the ultrasonic blade.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: April 23, 2024
    Assignee: Cilag GmbH International
    Inventors: Ryan M. Asher, Brian D. Black, John E. Brady, Joseph Dennis, Geni M. Giannotti, Bryce L. Heitman, Timothy S. Holland, Joseph E. Hollo, Andrew Kolpitcke, Amy M. Krumm, Jason R. Lesko, Matthew C. Miller, David A. Monroe, Ion V. Nicolaescu, Rafael J. Ruiz Ortiz, Matthew S. Schneider, Richard C. Smith, Shawn C. Snyder, Sarah A. Worthington, Monica L. Rivard, Fajian Zhang
  • Publication number: 20220262733
    Abstract: A package substrate for connecting together semiconductor devices with other semiconductor device packages. The package substrate includes an exposed core layer with at least one via exposing a conductive layer of the package substrate. A first portion of the package substrate may include a solder mask on top and bottom surfaces. A first semiconductor device may be connected to the first portion of the package substrate. Layers of a second portion of the package substrate are removed to expose a core layer and vias are created in the exposed core layer to expose the conductive layer. Conducive material at least partially filling the vias may be used to connect a semiconductor device package to the second portion of the package substrate. The semiconductor device packages may communicate through conductive layers in the package substrate. The package substrate may be used to connect the semiconductor packages to a motherboard.
    Type: Application
    Filed: May 6, 2022
    Publication date: August 18, 2022
    Inventor: Matthew Monroe
  • Patent number: 11328997
    Abstract: A package substrate for connecting together semiconductor devices with other semiconductor device packages. The package substrate includes an exposed core layer with at least one via exposing a conductive layer of the package substrate. A first portion of the package substrate may include a solder mask on top and bottom surfaces. A first semiconductor device may be connected to the first portion of the package substrate. Layers of a second portion of the package substrate are removed to expose a core layer and vias are created in the exposed core layer to expose the conductive layer. Conducive material at least partially filling the vias may be used to connect a semiconductor device package to the second portion of the package substrate. The semiconductor device packages may communicate through conductive layers in the package substrate. The package substrate may be used to connect the semiconductor packages to a motherboard.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: May 10, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Matthew Monroe
  • Patent number: 10777530
    Abstract: Semiconductor device packages for incorporation into semiconductor device assemblies may include a substrate including an array of electrically conductive elements located on a lower surface of the substrate. A window may extend through the substrate from the lower surface to an upper surface of the substrate. The array of electrically conductive elements may at least partially laterally surround a periphery of the window, and the substrate may extend laterally beyond the array of electrically conductive elements. At least a portion of a heat-management structure may be located within the window. At least a portion of an outer periphery of an underlying substrate may laterally overlap with an inner portion of the substrate defining the periphery of the window.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: September 15, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Matthew Monroe
  • Publication number: 20200227355
    Abstract: A package substrate for connecting together semiconductor devices with other semiconductor device packages. The package substrate includes an exposed core layer with at least one via exposing a conductive layer of the package substrate. A first portion of the package substrate may include a solder mask on top and bottom surfaces. A first semiconductor device may be connected to the first portion of the package substrate. Layers of a second portion of the package substrate are removed to expose a core layer and vias are created in the exposed core layer to expose the conductive layer. Conducive material at least partially filling the vias may be used to connect a semiconductor device package to the second portion of the package substrate. The semiconductor device packages may communicate through conductive layers in the package substrate. The package substrate may be used to connect the semiconductor packages to a motherboard.
    Type: Application
    Filed: March 26, 2020
    Publication date: July 16, 2020
    Inventor: Matthew Monroe
  • Patent number: 10629536
    Abstract: A package substrate for connecting together semiconductor devices with other semiconductor device packages. The package substrate includes an exposed core layer with at least one via exposing a conductive layer of the package substrate. A first portion of the package substrate may include a solder mask on top and bottom surfaces. A first semiconductor device may be connected to the first portion of the package substrate. Layers of a second portion of the package substrate are removed to expose a core layer and vias are created in the exposed core layer to expose the conductive layer. Conducive material at least partially filling the vias may be used to connect a semiconductor device package to the second portion of the package substrate. The semiconductor device packages may communicate through conductive layers in the package substrate. The package substrate may be used to connect the semiconductor packages to a motherboard.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: April 21, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Matthew Monroe
  • Publication number: 20190311987
    Abstract: A package substrate for connecting together semiconductor devices with other semiconductor device packages. The package substrate includes an exposed core layer with at least one via exposing a conductive layer of the package substrate. A first portion of the package substrate may include a solder mask on top and bottom surfaces. A first semiconductor device may be connected to the first portion of the package substrate. Layers of a second portion of the package substrate are removed to expose a core layer and vias are created in the exposed core layer to expose the conductive layer. Conducive material at least partially filling the vias may be used to connect a semiconductor device package to the second portion of the package substrate. The semiconductor device packages may communicate through conductive layers in the package substrate. The package substrate may be used to connect the semiconductor packages to a motherboard.
    Type: Application
    Filed: April 5, 2018
    Publication date: October 10, 2019
    Inventor: Matthew Monroe
  • Publication number: 20190051631
    Abstract: Semiconductor device packages for incorporation into semiconductor device assemblies may include a substrate including an array of electrically conductive elements located on a lower surface of the substrate. A window may extend through the substrate from the lower surface to an upper surface of the substrate. The array of electrically conductive elements may at least partially laterally surround a periphery of the window, and the substrate may extend laterally beyond the array of electrically conductive elements. At least a portion of a heat-management structure may be located within the window. At least a portion of an outer periphery of an underlying substrate may laterally overlap with an inner portion of the substrate defining the periphery of the window.
    Type: Application
    Filed: October 16, 2018
    Publication date: February 14, 2019
    Inventor: Matthew Monroe
  • Patent number: 10184562
    Abstract: A device includes an outer cylinder having a cylinder inner wall and a cylinder outer wall and at least one magnet disposed on or between the cylinder inner wall and the cylinder outer wall and a piston having a piston inner wall and a piston outer wall and at least one magnet disposed on or between the piston outer wall and the piston inner wall. In one embodiment, the piston is rotatable within the cylinder and slidably movable along an axis respective to the cylinder. The piston is also disposed within the cylinder such that the at least one magnet disposed on or between the cylinder inner wall and the cylinder outer wall is aligned with the at least one magnet disposed on or between the piston outer wall and the piston inner wall, substantially preventing the piston from rotating relative to the cylinder.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: January 22, 2019
    Assignee: Eaton Intelligent Power Limited
    Inventor: Matthew Monroe Kuhns
  • Patent number: 10121766
    Abstract: Semiconductor device packages for incorporation into semiconductor device assemblies may include a substrate including an array of electrically conductive elements located on a lower surface of the substrate. A window may extend through the substrate from the lower surface to an upper surface of the substrate. The array of electrically conductive elements may at least partially laterally surround a periphery of the window, and the substrate may extend laterally beyond the array of electrically conductive elements. Semiconductor devices may be supported on the upper surface of the substrate around a periphery of the array of electrically conductive elements. The semiconductor devices may be electrically connected to at least some of the electrically conductive elements of the array by routing elements extending from the semiconductor devices toward the window.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: November 6, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Matthew Monroe
  • Publication number: 20180005983
    Abstract: Semiconductor device packages for incorporation into semiconductor device assemblies may include a substrate including an array of electrically conductive elements located on a lower surface of the substrate. A window may extend through the substrate from the lower surface to an upper surface of the substrate. The array of electrically conductive elements may at least partially laterally surround a periphery of the window, and the substrate may extend laterally beyond the array of electrically conductive elements. Semiconductor devices may be supported on the upper surface of the substrate around a periphery of the array of electrically conductive elements. The semiconductor devices may be electrically connected to at least some of the electrically conductive elements of the array by routing elements extending from the semiconductor devices toward the window.
    Type: Application
    Filed: August 16, 2016
    Publication date: January 4, 2018
    Inventor: Matthew Monroe
  • Publication number: 20170108121
    Abstract: A device includes an outer cylinder having a cylinder inner wall and a cylinder outer wall and at least one magnet disposed on or between the cylinder inner wall and the cylinder outer wall and a piston having a piston inner wall and a piston outer wall and at least one magnet disposed on or between the piston outer wall and the piston inner wall. In one embodiment, the piston is rotatable within the cylinder and slidably movable along an axis respective to the cylinder. The piston is also disposed within the cylinder such that the at least one magnet disposed on or between the cylinder inner wall and the cylinder outer wall is aligned with the at least one magnet disposed on or between the piston outer wall and the piston inner wall, substantially preventing the piston from rotating relative to the cylinder.
    Type: Application
    Filed: June 2, 2015
    Publication date: April 20, 2017
    Applicant: Eaton Corporation
    Inventor: Matthew Monroe Kuhns
  • Patent number: D794140
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: August 8, 2017
    Inventor: Matthew Monroe