Patents by Inventor Matthew Moon

Matthew Moon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080019077
    Abstract: Disclosed is a method of fabricating a metal-insulator-metal (MIM) capacitor. In this method, a dielectric layer is formed above a lower conductor layer and an upper conductor layer is formed above the dielectric layer. The invention then forms an etch stop layer above the upper conductor layer and the dielectric layer, and forms a hardmask (silicon oxide hardmask, a silicon nitride hardmask, etc.) over the etch stop layer. Next, a photoresist is patterned above the hardmask, which allows the hardmask, the etch stop layer, the dielectric layer, and the lower conductor layer to be etched through the photoresist.
    Type: Application
    Filed: August 15, 2007
    Publication date: January 24, 2008
    Inventors: Douglas Coolbaugh, Ebenezer Eshun, Natalie Feilchenfeld, Michael Gautsch, Zhong-Xiang He, Matthew Moon, Vidhya Rahmachandran, Barbara Waterhouse
  • Publication number: 20070290272
    Abstract: A BEOL thin-film resistor adapted for flexible integration rests on a first layer of ILD. The thickness of the first layer of ILD and the resistor thickness combine to match the nominal design thickness of vias in the layer of concern. A second layer of ILD matches the resistor thickness and is planarized to the top surface of the resistor. A third layer of ILD has a thickness equal to the nominal value of the interconnections on this layer. Dual damascene interconnection apertures and apertures for making contact with the resistor are formed simultaneously, with the etch stop upper cap layer in the resistor protecting the resistive layer while the vias in the dual damascene apertures are formed.
    Type: Application
    Filed: August 29, 2007
    Publication date: December 20, 2007
    Inventors: Eric Coker, Douglas Coolbaugh, Ebenezer Eshun, Zhong-Xiang He, Matthew Moon, Anthony Stamper
  • Publication number: 20070187787
    Abstract: A pixel for an image sensor includes a photosensor located within a substrate. A patterned dielectric layer having an aperture registered with the photosensor is located over the substrate. A lens structure is located over the dielectric layer and also registered with the photosensor. A liner layer is located contiguously upon a top surface of the dielectric layer, and the sidewalls and bottom of the aperture. The liner layer provides for enhanced reflection for off-axis incoming light and enhanced capture thereof by the photosensor. When the aperture does not provide a dielectric layer border for a metallization layer embedded within the dielectric layer, an exposed edge of the metallization layer may be chamfered.
    Type: Application
    Filed: February 16, 2006
    Publication date: August 16, 2007
    Inventors: Kristin Ackerson, James Adkisson, John Ellis-Monaghan, Jeffrey Gambino, Timothy Hoague, Mark Jaffe, Robert Leidy, Matthew Moon, Richard Passel
  • Publication number: 20070166909
    Abstract: A BEOL thin-film resistor adapted for flexible integration rests on a first layer of ILD. The thickness of the first layer of ILD and the resistor thickness combine to match the nominal design thickness of vias in the layer of concern. A second layer of ILD matches the resistor thickness and is planarized to the top surface of the resistor. A third layer of ILD has a thickness equal to the nominal value of the interconnections on this layer. *Dual damascene interconnection apertures and apertures for making contact with the resistor are formed simultaneously, with the etch stop upper cap layer in the resistor protecting the resistive layer while the vias in the dual damascene apertures are formed.
    Type: Application
    Filed: January 19, 2006
    Publication date: July 19, 2007
    Inventors: Eric Coker, Douglas Coolbaugh, Ebenezer Eshun, Zhong-Xiang He, Matthew Moon, Anthony Stamper
  • Publication number: 20070158714
    Abstract: A MIM capacitor technique is described wherein bottom plates (electrodes) are composed of gate conductor material, and are formed in the same layer, in the same way, using the same masking and processing steps as transistor gates. The top plates (electrodes) are formed using a simple single-mask, single-damascene process. Electrical connections to both electrodes of the MIM capacitor are made via conventional BEOL metallization, requiring no additional dedicated process steps. The bottom plates (formed of gate conductor material) of the MIM capacitors overlie STI regions formed at the same time as STI regions between transistors. Method and apparatus are described.
    Type: Application
    Filed: November 21, 2005
    Publication date: July 12, 2007
    Applicant: International Business Machines Corporation
    Inventors: Ebenezer Eshun, Jessie Abbotts, Daniel Colello, Douglas Coolbaugh, Zhong-Xiang He, Matthew Moon, Charles Musante, Robert Rassel
  • Publication number: 20050272219
    Abstract: Disclosed is a method of fabricating a metal-insulator-metal (MIM) capacitor. In this method, a dielectric layer is formed above a lower conductor layer and an upper conductor layer is formed above the dielectric layer. The invention then forms an etch stop layer above the upper conductor layer and the dielectric layer, and forms a hardmask (silicon oxide hardmask, a silicon nitride hardmask, etc.) over the etch stop layer. Next, a photoresist is patterned above the hardmask, which allows the hardmask, the etch stop layer, the dielectric layer, and the lower conductor layer to be etched through the photoresist.
    Type: Application
    Filed: June 4, 2004
    Publication date: December 8, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Douglas Coolbaugh, Ebenezer Eshun, Natalie Feilchenfeld, Michael Gautsch, Zhong-Xiang He, Matthew Moon, Vidhya Ramachandran, Barbara Waterhouse