Patents by Inventor Matthew Park

Matthew Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190250165
    Abstract: A compound of formula (I): as described herein and methods and uses thereof as for mass tagging a biosensor or biologically active material.
    Type: Application
    Filed: January 11, 2019
    Publication date: August 15, 2019
    Inventors: Mark Nitz, Landon J. Edgar, Bradly G. Wouters, David Hedley, Lisa M. Willis, Matthew A. Lumba, Hanuel Park, Ravi N. Vellanki
  • Patent number: 10372396
    Abstract: An aspect provides a method, including: receiving, from a wireless display device, one or more beacons using a receiver of an information handling device; using, at the information handling device, the one or more beacons to determine one or more wireless display device characteristics; initiating, at the information handling device, one of a plurality of wireless connection protocols determined based on the one or more wireless display device characteristics; establishing, using a communication module of the information handling device, a wireless connection with the wireless display device; and transmitting, with the communication module of the information handling device, data for display to the wireless display device. Other aspects are described and claimed.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: August 6, 2019
    Assignee: Lenovo ( Singapore) Pte. Ltd.
    Inventors: Steve Richard Perrin, Scott Edwards Kelso, Matthew Price Roper, Matthew Lloyd Hagenbuch, Song Wang, Bradley Park Strazisar
  • Publication number: 20190234617
    Abstract: A connected oven, including a set of in-cavity sensors and a processor configured to automatically identify foodstuff within the cooking cavity, based on the sensor measurements; and automatically operate the heating element based on the foodstuff identity.
    Type: Application
    Filed: April 10, 2019
    Publication date: August 1, 2019
    Inventors: Nikhil Bhogal, Matthew Van Horn, Seunghoon Park, Ravishankar Sivalingam, Christopher Russell Clark
  • Publication number: 20190229127
    Abstract: An array of elevationally-extending strings of memory cells, where the memory cells individually comprise a programmable charge storage transistor, comprises a substrate comprising a first region containing memory cells and a second region not containing memory cells laterally of the first region. The first region comprises vertically-alternating tiers of insulative material and control gate material. The second region comprises vertically-alternating tiers of different composition insulating materials laterally of the first region. A channel pillar comprising semiconductive channel material extends elevationally through multiple of the vertically-alternating tiers within the first region. Tunnel insulator, programmable charge storage material, and control gate blocking insulator are between the channel pillar and the control gate material of individual of the tiers of the control gate material within the first region.
    Type: Application
    Filed: April 2, 2019
    Publication date: July 25, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Justin B. Dorhout, Kunal R. Parekh, Matthew Park, Joseph Neil Greeley, Chet E. Carter, Martin C. Roberts, Indra V. Chary, Vinayak Shamanna, Ryan Meyer, Paolo Tessariol
  • Patent number: 10346910
    Abstract: In a system for executing transaction requests, a received request for a transaction in an item is delayed prior to matching that request with another request for transaction in that item by a delay based on a communication delay and/or a processing delay. The communication delay represents the time required to receive updated information about the item and the processing delay represents the time required to compute an updated item price using the received updated information.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: July 9, 2019
    Assignee: IEX GROUP, INC.
    Inventors: Bradley Katsuyama, John Schwall, Robert Park, Ronan Ryan, Benjamin Aisen, Daniel Aisen, Donald Bollerman, Francis Chung, Stanley Feldman, Tara McKee, Bilie Zhao, James Michael Cape, David Lauer, Allen Zhang, Blair Livingston, Matthew Norbert Trudeau, Zoran Perkov
  • Patent number: 10325585
    Abstract: Ambient sound is converted into digital signals. A processor performs active noise cancellation and/or a transformation operation that is distinct from the active noise cancellation on the digital signals. The active noise cancellation and the transformation operation transform the digital signals into modified digital signals. The modified digital signals are converted into modified analog signals. The modified analog signals are outputted as audio waves. An interior microphone is configured to output an output signal to the processor in response to receiving the modified analog signals. In response to receiving the output signal from the interior microphone, the processor is configured to determine whether the modified digital signals produce desired audio waves.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: June 18, 2019
    Assignee: Dolby Laboratories Licensing Corporation
    Inventors: Jeffrey Baker, Anthony Parks, Sal Gregory Garcia, Thomas Ezekiel Burgess, Matthew Fumio Yamamoto, Nils Jacob Palmborg, Noah Kraft, Richard Fritz Lanman, III, Daniel C. Wiggins
  • Patent number: 10263007
    Abstract: An array of elevationally-extending strings of memory cells, where the memory cells individually comprise a programmable charge storage transistor, comprises a substrate comprising a first region containing memory cells and a second region not containing memory cells laterally of the first region. The first region comprises vertically-alternating tiers of insulative material and control gate material. The second region comprises vertically-alternating tiers of different composition insulating materials laterally of the first region. A channel pillar comprising semiconductive channel material extends elevationally through multiple of the vertically-alternating tiers within the first region. Tunnel insulator, programmable charge storage material, and control gate blocking insulator are between the channel pillar and the control gate material of individual of the tiers of the control gate material within the first region.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: April 16, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Justin B. Dorhout, Kunal R. Parekh, Matthew Park, Joseph Neil Greeley, Chet E. Carter, Martin C. Roberts, Indra V. Chary, Vinayak Shamanna, Ryan Meyer, Paolo Tessariol
  • Publication number: 20190081061
    Abstract: A device comprises an array of elevationally-extending transistors and a circuit structure adjacent and electrically coupled to the elevationally-extending transistors of the array. The circuit structure comprises a stair step structure comprising vertically-alternating tiers comprising conductive steps that are at least partially elevationally separated from one another by insulative material. Operative conductive vias individually extend elevationally through one of the conductive steps at least to a bottom of the vertically-alternating tiers and individually electrically couple to an electronic component below the vertically-alternating tiers. Dummy structures individually extend elevationally through one of the conductive steps at least to the bottom of the vertically-alternating tiers. Methods are also disclosed.
    Type: Application
    Filed: September 14, 2017
    Publication date: March 14, 2019
    Inventors: Paolo Tessariol, Justin B. Dorhout, Indra V. Chary, Jun Fang, Matthew Park, Zhiqiang Xie, Scott D. Stull, Daniel Osterberg, Jason Reece, Jian Li
  • Publication number: 20190067306
    Abstract: A semiconductor device structure that comprises tiers of alternating dielectric levels and conductive levels and a carbon-doped silicon nitride over the tiers of the staircase structure. The carbon-doped silicon nitride excludes silicon carbon nitride. A method of forming the semiconductor device structure comprises forming stairs in a staircase structure comprising alternating dielectric levels and conductive levels. A carbon-doped silicon nitride is formed over the stairs, an oxide material is formed over the carbon-doped silicon nitride, and openings are formed in the oxide material. The openings extend to the carbon-doped silicon nitride. The carbon-doped silicon nitride is removed to extend the openings into the conductive levels of the staircase structure. Additional methods are disclosed.
    Type: Application
    Filed: August 24, 2017
    Publication date: February 28, 2019
    Inventors: Jun Fang, Fei Wang, Saniya Rathod, Rutuparna Narulkar, Matthew Park, Matthew J. King
  • Publication number: 20190043890
    Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. Vertically-stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus.
    Type: Application
    Filed: October 11, 2018
    Publication date: February 7, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Justin B. Dorhout, Fei Wang, Chet E. Carter, Ian Laboriante, John D. Hopkins, Kunal Shrotri, Ryan Meyer, Vinayak Shamanna, Kunal R. Parekh, Martin C. Roberts, Matthew Park
  • Patent number: 10157933
    Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. Vertically-stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: December 18, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Justin B. Dorhout, Fei Wang, Chet E. Carter, Ian Laboriante, John D. Hopkins, Kunal Shrotri, Ryan Meyer, Vinayak Shamanna, Kunal R. Parekh, Martin C. Roberts, Matthew Park
  • Publication number: 20180286879
    Abstract: An array of elevationally-extending strings of memory cells, where the memory cells individually comprise a programmable charge storage transistor, comprises a substrate comprising a first region containing memory cells and a second region not containing memory cells laterally of the first region. The first region comprises vertically-alternating tiers of insulative material and control gate material. The second region comprises vertically-alternating tiers of different composition insulating materials laterally of the first region. A channel pillar comprising semiconductive channel material extends elevationally through multiple of the vertically-alternating tiers within the first region. Tunnel insulator, programmable charge storage material, and control gate blocking insulator are between the channel pillar and the control gate material of individual of the tiers of the control gate material within the first region.
    Type: Application
    Filed: June 7, 2018
    Publication date: October 4, 2018
    Applicant: Micron Technology, Inc.
    Inventors: Justin B. Dorhout, Kunal R. Parekh, Matthew Park, Joseph Neil Greeley, Chet E. Carter, Martin C. Roberts, Indra V. Chary, Vinayak Shamanna, Ryan Meyer, Paolo Tessariol
  • Patent number: 10070880
    Abstract: A device for gripping tissue that is inside of a patient for use in delivering therapy is provided. The device may include a first gear that rotates and that engages the tissue. A second gear that also rotates may be included and may likewise engage the tissue. A spacing mechanism may be included in the device that adjusts the spacing between the first and second gears such that the first and second gears are moved closer to one another and moved farther from one another.
    Type: Grant
    Filed: April 13, 2014
    Date of Patent: September 11, 2018
    Assignee: Actuated Medical, Inc.
    Inventors: Roger B Bagwell, Brian Matthew Park, Casey A Scruggs, Kevin A Snook
  • Publication number: 20180190587
    Abstract: A method of forming a semiconductor device assembly comprises forming tiers comprising conductive structures and insulating structures in a stacked arrangement over a substrate. Portions of the tiers are selectively removed to form a stair step structure comprising a selected number of steps exhibiting different widths corresponding to variances in projected error associated with forming the steps. Contact structures are formed on the steps of the stair step structure. Semiconductor device structures and semiconductor devices are also described.
    Type: Application
    Filed: February 27, 2018
    Publication date: July 5, 2018
    Inventors: Matthew Park, Adam L. Olson, Jixin Yu
  • Patent number: 10014309
    Abstract: An array of elevationally-extending strings of memory cells, where the memory cells individually comprise a programmable charge storage transistor, comprises a substrate comprising a first region containing memory cells and a second region not containing memory cells laterally of the first region. The first region comprises vertically-alternating tiers of insulative material and control gate material. The second region comprises vertically-alternating tiers of different composition insulating materials laterally of the first region. A channel pillar comprising semiconductive channel material extends elevationally through multiple of the vertically-alternating tiers within the first region. Tunnel insulator, programmable charge storage material, and control gate blocking insulator are between the channel pillar and the control gate material of individual of the tiers of the control gate material within the first region.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: July 3, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Justin B. Dorhout, Kunal R. Parekh, Matthew Park, Joseph Neil Greeley, Chet E. Carter, Martin C. Roberts, Indra V. Chary, Vinayak Shamanna, Ryan Meyer, Paolo Tessariol
  • Publication number: 20180109609
    Abstract: A method of facilitating peer-to-peer connection involves transmitting, by a first peer device, an identification of the first peer device and information regarding its capabilities. The information regarding its capabilities including a list of transmission channels that the first peer device is capable of supporting, an indication of which transmission channels the first peer device is capable of supporting as a group owner, and/or an indication of which transmission channels the first peer device is capable of supporting as a client. The first peer device receives from a second peer device, an identification of the second peer device and information regarding its capabilities including a list of transmission channels that the second peer device is capable of supporting. The first peer device and the second peer device then negotiate which of the first and second peer devices should be the group owner and which should be the client.
    Type: Application
    Filed: October 17, 2017
    Publication date: April 19, 2018
    Inventor: Matthew Parks
  • Publication number: 20180047739
    Abstract: An array of elevationally-extending strings of memory cells, where the memory cells individually comprise a programmable charge storage transistor, comprises a substrate comprising a first region containing memory cells and a second region not containing memory cells laterally of the first region. The first region comprises vertically-alternating tiers of insulative material and control gate material. The second region comprises vertically-alternating tiers of different composition insulating materials laterally of the first region. A channel pillar comprising semiconductive channel material extends elevationally through multiple of the vertically-alternating tiers within the first region. Tunnel insulator, programmable charge storage material, and control gate blocking insulator are between the channel pillar and the control gate material of individual of the tiers of the control gate material within the first region.
    Type: Application
    Filed: August 9, 2016
    Publication date: February 15, 2018
    Inventors: Justin B. Dorhout, Kunal R. Parekh, Matthew Park, Joseph Neil Greeley, Chet E. Carter, Martin C. Roberts, Indra V. Chary, Vinayak Shamanna, Ryan Meyer, Paolo Tessariol
  • Patent number: 9835408
    Abstract: The invention is a two-point firearm carrying apparatus attachable to a long gun having a first arm and a second arm. A spring with hooked ends attached to D rings on the arms is covered by a canvass sheath. The spring compresses and expands to allow sighting and use of the gun, and also to hold the sling against the chest when being transported. The first and second arms are adjustable in length depending upon the height and girth of the user.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: December 5, 2017
    Inventor: Matthew Parks
  • Publication number: 20170301685
    Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. Vertically-stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus.
    Type: Application
    Filed: April 19, 2016
    Publication date: October 19, 2017
    Inventors: Justin B. Dorhout, Fei Wang, Chet E. Carter, Ian Laboriante, John D. Hopkins, Kunal Shrotri, Ryan Meyer, Vinayak Shamanna, Kunal R. Parekh, Martin C. Roberts, Matthew Park
  • Publication number: 20170284766
    Abstract: The invention is a two-point firearm carrying apparatus attachable to a long gun having a first arm and a second arm. A spring with hooked ends attached to D rings on the arms is covered by a canvass sheath. The spring compresses and expands to allow sighting and use of the gun, and also to hold the sling against the chest when being transported. The first and second arms are adjustable in length depending upon the height and girth of the user.
    Type: Application
    Filed: June 16, 2017
    Publication date: October 5, 2017
    Inventor: Matthew Parks