Abstract: A flow cell for measuring the color properties of a liquid flowing therethrough using interrogating radiation at a predetermined wavelength has a thin partition mounted in spaced relationship between both a window and a base of the cell. The partition and the window define an air cavity therebetween. The spacing between the partition and the window is such that evanescent coupling of radiation reflected from the liquid into the material of the window is prevented. The cell has a pressurized fluid inflow channel and a pressurized fluid outflow channel formed therein. Each of the inflow and outflow channels communicates with the air cavity. The inflow and outflow channels are sized to pass a pressurized fluid, such as pressurized air, through the air cavity such that, in use, the spaced relationship between the partition and the window is maintained by pressurized fluid in the air cavity.

Abstract: The present invention concerns a probe for measuring hydrogen concentration in molten metals comprising a probe body and a hydrogen sensor. The sensor structure is based on a sensor body having a wall within which a sealed cavity is defined. The cavity contains a solid reference material for generating a reference partial pressure of hydrogen within the cavity. At least a portion of the wall of the cavity is formed from a solid electrolyte material carrying a measurement electrode on a surface of the solid electrolyte outside the cavity and a reference electrode on a surface of the solid electrolyte within the cavity, exposed to the reference partial pressure of hydrogen. An electrical conductor extends from the reference electrode through the wall of the cavity to an external surface of the sensor body. The probe body comprises a chamber for receiving the sensor and a reference-signal connection for connecting to the electrical conductor when the sensor is received in the chamber.

Abstract: A recumbent exercise device which provides lower body, upper body and cardiovascular conditioning is disclosed. A pair of leg assemblies and a pair of arm assemblies are pivotally supported by the frame for movement about a transverse pivot axis. The arm and leg assemblies each includes an upward and forward extending lever with the leg assemblies terminating in pedals and the arm assemblies terminating in handles. The arm and leg assemblies are connected to each other for contralateral movement. A resistance mechanism is positioned substantially between the legs of a user.

Abstract: A data processing apparatus communicates data bits on a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processing apparatus comprises a parity interleaver operable to perform parity interleaving on Low Density Parity Check (LDPC) encoded data bits obtained by performing LDPC encoding according to a parity check matrix of an LDPC code including a parity matrix corresponding to parity bits of the LDPC code, the parity matrix having a stepwise structure, so that a parity bit of the LDPC encoded data bits is interleaved to a different parity bit position. A mapping unit maps the parity interleaved bits onto data symbols corresponding to modulation symbols of a modulation scheme of the OFDM sub-carrier signals.

Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.

Abstract: A data processing apparatus is arranged to map input data symbols to be communicated onto a predetermined number of sub-carrier signals of Orthogonal Frequency Division Multiplexed OFDM symbols. The predetermined number of sub-carrier signals is determined in accordance with one of a plurality of operating modes and the input data symbols are divided into first sets of input data symbols and second sets of input data symbols.

Abstract: A data processor maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. A generator polynomial for the linear feedback shift register is R?i[8]=R?i?1[0]?R?i?1[4], and a permutation code is provided for permuting the order of the content of the register stages.

Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.

Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. The linear feedback shift register has ten register stages with a generator polynomial for the linear feedback shift register of R?i[9]=R?i?1[0] ?R?i?1[3], and the permutation code forms, with an additional bit, an eleven bit address.

Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. The linear feedback shift register has eleven register stages with a generator polynomial for the linear feedback shift register of R?i[10]=R?i?1[0]?R?i?1[2], and the permutation code forms, with an additional bit, a twelve bit address.

Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. The linear feedback shift register has twelve register stages with a generator polynomial for the linear feedback shift register of R?i[11]=R?i-1[0]R?i-1[1]R?i-1[4]R?i-1[6], and the permutation code forms, with an additional bit, a thirteen bit address.

Abstract: A system for acquiring and processing data for use by a clinical information system includes an interface processor for automatically receiving patient clinical data from multiple different sources. The interface processor parses clinical data received from an individual source to identify data elements indicating clinical data type as well as an associated time, stage, value and unit of measure. An adaptive data processor automatically adaptively processes the clinical data received from the individual source to provide processed clinical data accommodating absence of a value of at least one of the data elements by substituting at least one of, (a) a null value, (b) a zero value and (c) a default value for an absent data element. A storage processor stores the processed clinical data in a repository and retrieves a selectable plurality of the data elements for reproduction in an adaptively selectable presentation.

Abstract: The present application relates to compositions of modified toxins exhibiting reduced immunogenicity and reduced binding to vascular endothelium or vascular endothelial cells, thereby reducing the incidence of Vascular Leak Syndrome. Also provided are polypeptide toxophores from a modified diphtheria toxin, where modifications are in at least one amino acid residue of at least one T-cell epitope. Another aspect relates to a polypeptide toxophore from a modified diphtheria toxin, where modifications are in at least one amino acid residue of at least one T-cell epitope and at least one amino acid residue of at least one VLS motif of an unmodified native diphtheria toxin. Another aspect relates to a fusion protein which comprises a modified diphtheria toxin and a non-diphtheria toxin fragment that is a cell binding portion. Another aspect relates to the use of a modified diphtheria toxin for the treatment of a malignant disease or a non-malignant disease.

Abstract: A system and process for interacting with a system in an insecure state is described. Before logging into a secure state of a computer system, a user is able to access limited information including calendar information regarding meetings for that day and the like. In some aspects of the invention, a user may interact with a displayed note pad for receiving handwritten or typed notes. Aspects of the described system and method permit a user to quickly review or interact with a computer prior to logging into a secured state of the computer system.

Abstract: An electrician's vest provides a more convenient vest configuration and facilitates easy access to the tools and supplies stored therein. The vest also incorporates a carrying handle and reinforcement webbing to increase the stiffness of the vest. The vest includes a back brace or back support belt which is allowed to move relative to the vest to keep the support brace in a proper position on the user's lower back while still allowing adequate freedom of movement.

Abstract: A branch target buffer is provided which maintains its entries across context switches within a virtually addressed system. Branch mispredictions are detected for individual entries within the branch target buffer and those individual entries are invalidated.

Abstract: A branch prediction mechanism includes a history value register storing a history value which is used to address into a history buffer from which a plurality of prediction values are read and stored into a prediction value store. The one or more prediction values to be used with a potential branch instruction are selected from the prediction values store using a multiplexer switched by a branch predicting portion of a fetch address. The history buffer is only read when the history value changes whereas the prediction values store is read each time a potential branch instruction is identified requiting a prediction value to be associated with it. The reduced duty cycle of the history buffer saves power.

Abstract: Methods, systems, and computer program products are provided for controlling a GUI display for a plug-in in an application supporting plug-ins. Embodiments include receiving, at run time, in the application from the plug-in a request to display a GUI object; responsive to the request, retrieving an XML representation of the GUI object; and displaying the GUI object in dependence upon the retrieved XML representation of the GUI object. Typical embodiments also include receiving from the plug-in a request to retrieve user input responsive to the GUI object; and returning to the plug-in responsive user input.

Abstract: Operating an integrated development environment in a data processing system comprising running a source code editor, displaying source code in a graphical interface of the source code editor, displaying at least one cross-reference marker, the at least one cross-reference marker indicating crosscutting in the source code, receiving an input, changing one or more cross-reference markers, and highlighting the one or more changed cross-reference marker.