Patents by Inventor Matthew Plonski
Matthew Plonski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Methods and apparatus for efficient complex long multiplication and covariance matrix implementation
Patent number: 9075651Abstract: Efficient computation of complex long multiplication results and an efficient calculation of a covariance matrix are described. A parallel array VLIW digital signal processor is employed along with specialized complex long multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs may be used allowing the complex multiplication pipeline hardware to be efficiently used.Type: GrantFiled: September 13, 2012Date of Patent: July 7, 2015Assignee: Altera CorporationInventors: Gerald George Pechanek, Ricardo Rodriguez, Matthew Plonski, David Strube, Kevin Coopman -
Publication number: 20130006617Abstract: Techniques for implementing vocoders in parallel digital signal processors are described. A preferred approach is implemented in conjunction with the BOPS® Manifold Array (ManArray™) processing architecture so that in an array of N parallel processing elements, N channels of voice communication are processed in parallel. Techniques for forcing vocoder processing of one data-frame to take the same number of cycles are described. Improved throughput and lower clock rates can be achieved.Type: ApplicationFiled: September 13, 2012Publication date: January 3, 2013Applicant: ALTERA CORPORATIONInventors: Ali Soheil Sadri, Navin Jaffer, Anissim A. Silivra, Bin Huang, Matthew Plonski
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Methods and Apparatus for Efficient Complex Long Multiplication and Covariance Matrix Implementation
Publication number: 20130007421Abstract: Efficient computation of complex long multiplication results and an efficient calculation of a covariance matrix are described. A parallel array VLIW digital signal processor is employed along with specialized complex long multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs may be used allowing the complex multiplication pipeline hardware to be efficiently used.Type: ApplicationFiled: September 13, 2012Publication date: January 3, 2013Applicant: ALTERA CORPORATIONInventors: Gerald G. Pechanek, Ricardo Rodriguez, Matthew Plonski, David Strube, Kevin Coopman -
Patent number: 8340960Abstract: Techniques for implementing vocoders in parallel digital signal processors are described. A preferred approach is implemented in conjunction with the BOPS® Manifold Array (ManArray™) processing architecture so that in an array of N parallel processing elements, N channels of voice communication are processed in parallel. Techniques for forcing vocoder processing of one data-frame to take the same number of cycles are described. Improved throughput and lower clock rates can be achieved.Type: GrantFiled: June 16, 2009Date of Patent: December 25, 2012Assignee: Altera CorporationInventors: Ali Soheil Sadri, Navin Jaffer, Anissim A. Silivra, Bin Huang, Matthew Plonski
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Methods and apparatus for efficient complex long multiplication and covariance matrix implementation
Patent number: 8335812Abstract: Efficient computation of complex long multiplication results and an efficient calculation of a covariance matrix are described. A parallel array VLIW digital signal processor is employed along with specialized complex long multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs may be used allowing the complex multiplication pipeline hardware to be efficiently used.Type: GrantFiled: January 19, 2010Date of Patent: December 18, 2012Assignee: Altera CorporationInventors: Gerald George Pechanek, Ricardo Rodriguez, Matthew Plonski, David Strube, Kevin Coopman -
Methods and apparatus for efficient complex long multiplication and covariance matrix implementation
Publication number: 20100121899Abstract: Efficient computation of complex long multiplication results and an efficient calculation of a covariance matrix are described. A parallel array VLIW digital signal processor is employed along with specialized complex long multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs may be used allowing the complex multiplication pipeline hardware to be efficiently used.Type: ApplicationFiled: January 19, 2010Publication date: May 13, 2010Applicant: Altera CorporationInventors: Gerald G. Pechanek, Ricardo Rodriguez, Matthew Plonski, David Strube, Kevin Coopman -
Methods and apparatus for efficient complex long multiplication and covariance matrix implementation
Patent number: 7680873Abstract: Efficient computation of complex long multiplication results and an efficient calculation of a covariance matrix are described. A parallel array VLIW digital signal processor is employed along with specialized complex long multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs may be used allowing the complex multiplication pipeline hardware to be efficiently used.Type: GrantFiled: May 22, 2006Date of Patent: March 16, 2010Assignee: Altera CorporationInventors: Gerald George Pechanek, Ricardo Rodriguez, Matthew Plonski, David Strube, Kevin Coopman -
Publication number: 20090259463Abstract: Techniques for implementing vocoders in parallel digital signal processors are described. A preferred approach is implemented in conjunction with the BOPS® Manifold Array (ManArray™) processing architecture so that in an array of N parallel processing elements, N channels of voice communication are processed in parallel. Techniques for forcing vocoder processing of one dataframe to take the same number of cycles are described. Improved throughput and lower clock rates can be achieved.Type: ApplicationFiled: June 16, 2009Publication date: October 15, 2009Applicant: Altera CorporationInventors: Ali Soheil Sadri, Navin Jaffer, Anissim A. Silivra, Bin Huang, Matthew Plonski
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Patent number: 7565287Abstract: Techniques for implementing vocoders in parallel digital signal processors are described. A preferred approach is implemented in conjunction with the BOPS® Manifold Array (ManArray™) processing architecture so that in an array of N parallel processing elements, N channels of voice communication are processed in parallel. Techniques for forcing vocoder processing of one data-frame to take the same number of cycles are described. Improved throughput and lower clock rates can be achieved.Type: GrantFiled: December 20, 2005Date of Patent: July 21, 2009Assignee: Altera CorporationInventors: Ali Soheil Sadri, Navin Jaffer, Anissim A. Silivra, Bin Huang, Matthew Plonski
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Methods and apparatus for efficient complex long multiplication and covariance matrix implementation
Publication number: 20060224656Abstract: Efficient computation of complex long multiplication results and an efficient calculation of a covariance matrix are described. A parallel array VLIW digital signal processor is employed along with specialized complex long multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs may be used allowing the complex multiplication pipeline hardware to be efficiently used.Type: ApplicationFiled: May 22, 2006Publication date: October 5, 2006Applicant: PTS CorporationInventors: Gerald Pechanek, Ricardo Rodriguez, Matthew Plonski, David Strube, Kevin Coopman -
Methods and apparatus for efficient complex long multiplication and covariance matrix implementation
Patent number: 7072929Abstract: A digital signal processor for computing various types of complex multiplication is described. The digital signal processor operates in conjunction with registers, a multiplier, an adder, and a multiplexer The Registers store first and second complex operands. The multiplier simultaneously performs multiplications to produce each combination of products between the real and imaginary terms of the first and second complex operands. The multiplexer selects which produced products are added to or subtracted from each other based on the type of complex multiplication being performed. The adder simultaneously performs additions and subtractions, if necessary, to produce both real and imaginary results depending on whether the type of complex multiplication being performed is a conjugated operation. The registers store the results of the complex multiplication.Type: GrantFiled: November 1, 2001Date of Patent: July 4, 2006Assignee: PTS CorporationInventors: Gerald G. Pechanek, Ricardo Rodriguez, Matthew Plonski, David Strube, Kevin Coopman -
Publication number: 20060100865Abstract: Techniques for implementing vocoders in parallel digital signal processors are described. A preferred approach is implemented in conjunction with the BOPS® Manifold Array (ManArray™) processing architecture so that in an array of N parallel processing elements, N channels of voice communication are processed in parallel. Techniques for forcing vocoder processing of one data-frame to take the same number of cycles are described. Improved throughput and lower clock rates can be achieved.Type: ApplicationFiled: December 20, 2005Publication date: May 11, 2006Applicant: PTS CorporationInventors: Ali Sadri, Navin Jaffer, Anissim Silivra, Bin Huang, Matthew Plonski
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Patent number: 7003450Abstract: Techniques for implementing vocoders in parallel digital signal processors are described. A preferred approach is implemented in conjunction with the BOPS® Manifold Array (ManArray™) processing architecture so that in an array of N parallel processing elements, N channels of voice communication are processed in parallel. Techniques for forcing vocoder processing of one data-frame to take the same number of cycles are described. Improved throughput and lower clock rates can be achieved.Type: GrantFiled: October 19, 2001Date of Patent: February 21, 2006Assignee: PTS CorporationInventors: Ali Soheil Sadri, Navin Jaffer, Anissim A. Silivra, Bin Huang, Matthew Plonski
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Methods and apparatus for efficient complex long multiplication and covariance matrix implementation
Publication number: 20020169813Abstract: Efficient computation of complex long multiplication results and an efficient calculation of a covariance matrix are described. A parallel array VLIW digital signal processor is employed along with specialized complex long multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs may be used allowing the complex multiplication pipeline hardware to be efficiently used.Type: ApplicationFiled: November 1, 2001Publication date: November 14, 2002Applicant: BOPS, Inc.Inventors: Gerald G. Pechanek, Ricardo Rodriguez, Matthew Plonski, David Strube, Kevin Coopman -
Publication number: 20020165709Abstract: Techniques for implementing vocoders in parallel digital signal processors are described. A preferred approach is implemented in conjunction with the BOPS® Manifold Array (ManArray™) processing architecture so that in an array of N parallel processing elements, N channels of voice communication are processed in parallel. Techniques for forcing vocoder processing of one data-frame to take the same number of cycles are described. Improved throughput and lower clock rates can be achieved.Type: ApplicationFiled: October 19, 2001Publication date: November 7, 2002Inventors: Ali Soheil Sadri, Navin Jaffer, Anissim A. Silivra, Bin Huang, Matthew Plonski