Patents by Inventor Matthew Pond
Matthew Pond has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11743028Abstract: Systems and methods for protecting block cipher computation operations, from external monitoring attacks.Type: GrantFiled: September 1, 2020Date of Patent: August 29, 2023Assignee: Cryptography Research, Inc.Inventors: Jean-Michel Cioranesco, Elena Trichina, Elke De Mulder, Matthew Pond Baker
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Patent number: 11539509Abstract: Disclosed is a method and a system to execute the method to perform a first hashing operation to compute a first hash value, store the first hash value in a plurality of output registers, store a second message in a plurality of input registers, perform a first iteration of a second hashing operation, with an input to the second hashing operation including the second message and the first hash value, determine that a first portion of the second message, stored in a first register of the plurality of input registers, has been processed in course of the second hashing operation, and move a first portion of the first hash value stored in a first register of the plurality of output registers to the first register of the plurality of input registers.Type: GrantFiled: January 27, 2021Date of Patent: December 27, 2022Assignee: Cryptography Research, Inc.Inventors: Michael Hutter, Matthew Pond Baker
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Patent number: 11463236Abstract: An indication of a mode of operation to be performed with a block cipher may be received. Logic associated with the block cipher may be configured based on the indicated mode of operation to be performed with the block cipher. Furthermore, an input data and a mask data may be received. The input data may be combined with the mask data to generate a masked input data based on the configured logic. The masked input data may be provided to the block cipher based on the configured logic and an output data may be generated with the block cipher based on the provided masked input data.Type: GrantFiled: December 4, 2017Date of Patent: October 4, 2022Assignee: CRYPTOGRAPHY RESEARCH, INC.Inventors: Rodrigo Portella do Canto, Elke De Mulder, Pankaj Rohatgi, Matthew Pond Baker
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Patent number: 11353504Abstract: A first plurality of logic gates and a second plurality of logic gates may be associated with a symmetric configuration. A first output at a first value may be generated by the first plurality of logic gates based on a first portion of input signals. A second output may be generated by the second plurality of logic gates at the first value based on a second portion of the input signals. A subsequent first output at a particular value may be generated by the first plurality of logic gates based on a first portion of a second plurality of input signals and a subsequent second output may be generated by the second plurality of logic gates based on a second portion of the second plurality of input signals. A value of the subsequent second output may be complementary to the particular value of the subsequent first output.Type: GrantFiled: June 26, 2020Date of Patent: June 7, 2022Assignee: CRYPTOGRAPHY RESEARCH, INC.Inventors: Michael Hutter, Matthew Pond Baker
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Publication number: 20220156666Abstract: Methods and systems include receiving invoice data associated with an open invoice under an account; determining an expected payment date for the open invoice by inputting the data to a prediction model derived from a machine learning technique; determining an expected payment date range under a confidence level for the open invoice based on the invoice data and the open invoice; determining a probability of receiving a payment for the open invoice by a predetermined date; and outputting the expected payment date, the expected payment date range under the confidence level, and the probability of receiving the payment for the open invoice by the predetermined date for risk management analysis.Type: ApplicationFiled: November 19, 2020Publication date: May 19, 2022Applicant: Fidelity Information Services, LLCInventors: Daniel Tantum, Minming Ding, Ying Ji, Xiaodan Pan, Sean Daley, Andrew Scharhag, Matthew Pond, Michael Shields
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Patent number: 11307253Abstract: An indication of an operating mode of an asynchronous circuit may be received. A determination may be made as to whether the operating mode of the asynchronous circuit corresponds to a self-test of the asynchronous circuit. In response to determining that the operating mode of the asynchronous circuit corresponds to the self-test, a first clock signal may be provided to a first portion of a self-test component in a feedback path of the asynchronous circuit and a second clock signal may be provided to a second portion of the self-test component in the feedback path of the asynchronous circuit. Furthermore, a test value may be generated based on the first clock signal and the second clock signal.Type: GrantFiled: December 29, 2020Date of Patent: April 19, 2022Assignee: Cryptography Research, Inc.Inventor: Matthew Pond Baker
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Patent number: 11115147Abstract: Embodiments of the present disclosure pertain to improved circuit and system architectures for identifying and managing operating statuses and faults in a system having multiple processing circuit chips. Each of the multiple processing circuit chips includes multiple signal rings, one to provide internal communications among circuitry within the circuit chip, and another with inter-chip communications circuitry to provide communications with neighboring circuit chips. One of the multiple processing circuit chips further includes external communications circuitry to provide communications with an external host.Type: GrantFiled: January 9, 2019Date of Patent: September 7, 2021Assignee: Groq, Inc.Inventors: Matthew Pond Baker, Srivathsa Dhruvanarayan, Boone Jared Severson
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Publication number: 20210226775Abstract: Disclosed is a method and a system to execute the method to perform a first hashing operation to compute a first hash value, store the first hash value in a plurality of output registers, store a second message in a plurality of input registers, perform a first iteration of a second hashing operation, with an input to the second hashing operation including the second message and the first hash value, determine that a first portion of the second message, stored in a first register of the plurality of input registers, has been processed in course of the second hashing operation, and move a first portion of the first hash value stored in a first register of the plurality of output registers to the first register of the plurality of input registers.Type: ApplicationFiled: January 27, 2021Publication date: July 22, 2021Inventors: Michael Hutter, Matthew Pond Baker
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Publication number: 20210190862Abstract: An indication of an operating mode of an asynchronous circuit may be received. A determination may be made as to whether the operating mode of the asynchronous circuit corresponds to a self-test of the asynchronous circuit. In response to determining that the operating mode of the asynchronous circuit corresponds to the self-test, a first clock signal may be provided to a first portion of a self-test component in a feedback path of the asynchronous circuit and a second clock signal may be provided to a second portion of the self-test component in the feedback path of the asynchronous circuit. Furthermore, a test value may be generated based on the first clock signal and the second clock signal.Type: ApplicationFiled: December 29, 2020Publication date: June 24, 2021Inventor: Matthew Pond Baker
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Patent number: 11018849Abstract: An integrated circuit may implement a masked substitution box that includes substitution function components, a decoder, and a logic component. Each of the substitution function components may receive a same input value and a different mask value and may generate a respective output mask value based on the same input value and respective different mask value The decoder may receive an input mask value and generate a decoded output value that is based on the received input mask value. The logic component may select one of the output mask values from one of the substitution function components based on the decoded output value.Type: GrantFiled: October 28, 2019Date of Patent: May 25, 2021Assignee: CRYPTOGRAPHY RESEARCH, INC.Inventors: Matthew Pond Baker, Elena Trichina, Jean-Michel Cioranesco, Michael Hutter
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Publication number: 20210058228Abstract: Systems and methods for protecting block cipher computation operations, from external monitoring attacks.Type: ApplicationFiled: September 1, 2020Publication date: February 25, 2021Inventors: Jean-Michel Cioranesco, Elena Trichina, Elke De Mulder, Matthew Pond Baker
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Patent number: 10911221Abstract: A first hash value is calculated by using a first input value that is stored in a first set of registers. The first hash value is then stored in a second set of registers. A second input value is stored in the first set of registers after calculating the first hash value. The second hash value is calculated based on the first hash value and the second input value. During the calculating of the second hash value, the first hash value is shifted from the second set of registers to a portion of the first set of registers when the calculating of the second hash value has reached a state where the portion of the first set of registers is no longer used to store the second input value.Type: GrantFiled: October 17, 2019Date of Patent: February 2, 2021Assignee: Cryptography Research, Inc.Inventors: Michael Hutter, Matthew Pond Baker
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Patent number: 10884058Abstract: An indication of an operating mode of an asynchronous circuit may be received. A determination may be made as to whether the operating mode of the asynchronous circuit corresponds to a self-test of the asynchronous circuit. In response to determining that the operating mode of the asynchronous circuit corresponds to the self-test, a first clock signal may be provided to a first portion of a self-test component in a feedback path of the asynchronous circuit and a second clock signal may be provided to a second portion of the self-test component in the feedback path of the asynchronous circuit. Furthermore, a test value may be generated based on the first clock signal and the second clock signal.Type: GrantFiled: February 23, 2018Date of Patent: January 5, 2021Assignee: Cryptography Research, Inc.Inventor: Matthew Pond Baker
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Publication number: 20200393510Abstract: A first plurality of logic gates and a second plurality of logic gates may be associated with a symmetric configuration. A first output at a first value may be generated by the first plurality of logic gates based on a first portion of input signals. A second output may be generated by the second plurality of logic gates at the first value based on a second portion of the input signals. A subsequent first output at a particular value may be generated by the first plurality of logic gates based on a first portion of a second plurality of input signals and a subsequent second output may be generated by the second plurality of logic gates based on a second portion of the second plurality of input signals. A value of the subsequent second output may be complementary to the particular value of the subsequent first output.Type: ApplicationFiled: June 26, 2020Publication date: December 17, 2020Inventors: Michael Hutter, Matthew Pond Baker
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Patent number: 10771235Abstract: Systems and methods for protecting block cipher computation operations, from external monitoring attacks.Type: GrantFiled: August 22, 2017Date of Patent: September 8, 2020Assignee: Cryptography Research Inc.Inventors: Jean-Michel Cioranesco, Elena Trichina, Elke De Mulder, Matthew Pond Baker
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Patent number: 10712385Abstract: A first plurality of logic gates and a second plurality of logic gates may be associated with a symmetric configuration. A first output at a first value may be generated by the first plurality of logic gates based on a first portion of input signals. A second output may be generated by the second plurality of logic gates at the first value based on a second portion of the input signals. A subsequent first output at a particular value may be generated by the first plurality of logic gates based on a first portion of a second plurality of input signals and a subsequent second output maybe generated by the second plurality of logic gates based on a second portion of the second plurality of input signals. A value of the subsequent second output may be complementary to the particular value of the subsequent first output.Type: GrantFiled: December 1, 2016Date of Patent: July 14, 2020Assignee: CRYPTOGRAPHY RESEARCH INC.Inventors: Michael Hutter, Matthew Pond Baker
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Publication number: 20200220643Abstract: Embodiments of the present disclosure pertain to improved circuit and system architectures for identifying and managing operating statuses and faults in a system having multiple processing circuit chips. Each of the multiple processing circuit chips includes multiple signal rings, one to provide internal communications among circuitry within the circuit chip, and another with inter-chip communications circuitry to provide communications with neighboring circuit chips. One of the multiple processing circuit chips further includes external communications circuitry to provide communications with an external host.Type: ApplicationFiled: January 9, 2019Publication date: July 9, 2020Inventors: Matthew Pond Baker, Srivathsa Dhruvanarayan, Boone Jared Severson
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Publication number: 20200127815Abstract: A first hash value is calculated by using a first input value that is stored in a first set of registers. The first hash value is then stored in a second set of registers. A second input value is stored in the first set of registers after calculating the first hash value. The second hash value is calculated based on the first hash value and the second input value. During the calculating of the second hash value, the first hash value is shifted from the second set of registers to a portion of the first set of registers when the calculating of the second hash value has reached a state where the portion of the first set of registers is no longer used to store the second input value.Type: ApplicationFiled: October 17, 2019Publication date: April 23, 2020Inventors: Michael Hutter, Matthew Pond Baker
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Publication number: 20200067695Abstract: An integrated circuit may implement a masked substitution box that includes substitution function components, a decoder, and a logic component. Each of the substitution function components may receive a same input value and a different mask value and may generate a respective output mask value based on the same input value and respective different mask value The decoder may receive an input mask value and generate a decoded output value that is based on the received input mask value. The logic component may select one of the output mask values from one of the substitution function components based on the decoded output value.Type: ApplicationFiled: October 28, 2019Publication date: February 27, 2020Inventors: Matthew Pond Baker, Elena Trichina, Jean-Michel Cioranesco, Michael Hutter
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Publication number: 20190349187Abstract: An indication of a mode of operation to be performed with a block cipher may be received. Logic associated with the block cipher may be configured based on the indicated mode of operation to be performed with the block cipher. Furthermore, an input data and a mask data may be received. The input data may be combined with the mask data to generate a masked input data based on the configured logic. The masked input data may be provided to the block cipher based on the configured logic and an output data may be generated with the block cipher based on the provided masked input data.Type: ApplicationFiled: December 4, 2017Publication date: November 14, 2019Inventors: Rodrigo Portella do Canto, Elke De Mulder, Pankaj Rohatgi, Matthew Pond Baker