Abstract: Embodiments of the invention include an orthopedic milling machine for preparing a glenoid bone. The milling machine uses a hub and a sleeve. The hub includes reliefs arranged to cut or mill the bone and the sleeve couples to the hub to transfer rotational motion to the hub. The hub has an axial bore sized to receive an orthopedic guide pin. The hub also has a lateral passage slot that allows the hub to move laterally towards the guide pin in order to place the guide pin within the axial bore.

Abstract: Embodiments of the invention include an orthopedic milling machine for preparing a glenoid bone. The milling machine uses a hub and a sleeve. The hub includes reliefs arranged to cut or mill the bone and the sleeve couples to the hub to transfer rotational motion to the hub. The hub has an axial bore sized to receive an orthopedic guide pin. The hub also has a lateral passage slot that allows the hub to move laterally towards the guide pin in order to place the guide pin within the axial bore.

Abstract: In a complex manufacturing environment for producing semiconductor devices, a predicted quality distribution in the form of a graded die forecast may be monitored with respect to changes in order to more efficiently identify factory disturbances. To this end, a predicted distribution obtained on the basis of electrical measurement data may be compared with a predicted yield distribution based on other production data. That is, an efficient automatic monitoring of the manufacturing environment may be accomplished with reduced probability of missing respective disturbance situations, since the large number of electrical parameters may be condensed into the predicted quality distribution.

Abstract: A method, apparatus and a system, for provided for performing a dynamic weighting technique for performing fault detection. The method comprises processing a workpiece and performing a fault detection analysis relating to the processing of the workpiece. The method further comprises determining a relationship of a parameter relating to the fault detection analysis to a detected fault and adjusting a weighting associated with the parameter based upon the relationship of the parameter to the detected fault.

Abstract: The present invention is generally directed to various methods and systems for dynamically adjusting metrology sampling based upon available metrology capacity. In one illustrative embodiment, the method comprises providing a metrology control unit that is adapted to determine a baseline metrology sampling rate for at least one metrology operation, determining available metrology capacity, and providing the determined available metrology capacity to the metrology control unit wherein the metrology control unit determines a new metrology sampling rate based upon the determined available metrology capacity.

Abstract: The present invention is generally directed to various methods and systems for prioritizing material to clear exception conditions. In one illustrative embodiment, the method includes providing a plurality of workpieces, each of the workpieces having an associated quantity of material that cannot be processed until the workpiece has been processed, and determining a priority for processing each of the plurality of workpieces based upon at least the associated quantity of material that cannot be processed.

Abstract: The present invention relates generally to exercising equipment, and more particularly, to an improved multi-use weight lifting apparatus. The present weight lifting apparatus comprises a frame (12), a vertical guide member (52), at least one horizontal guide member (46), a weight bearing bar (60), and a safety catch mechanism (70). This weight lifting apparatus allows a weight lifter to perform exercise with vertical and horizontal ranges of motion that simulate the natural motions of using free weights while providing safety mechanisms that are not available with free weights.

Abstract: The present invention is generally directed to various methods and systems for adaptive metrology sampling plans that may be employed to monitor various manufacturing processes. In one example, the method comprises creating a plurality of metrology sampling rules, assigning each of the metrology sampling rules a sampling weight value, identifying at least one workpiece that satisfies at least one of the metrology sampling rules, assigning the sampling weight value for each of the satisfied metrology sampling rules with the identified workpieces that satisfy the rules, and indicating a metrology operation should be performed when a cumulative total of the sampling weight values is at least equal to a pre-established trigger value.

Abstract: The present invention is directed to a method of controlling an etching process used to form a gate electrode on a semiconductor device. In one embodiment, the method comprises forming a layer of silicon dioxide above a semiconducting substrate, and forming a layer of polysilicon above the layer of silicon dioxide. The method further comprises sensing a thickness of the layer of polysilicon and adjusting, based upon the sensed thickness of said layer of polysilicon, at least one parameter of an etching process to be performed on said layer of polysilicon to define a gate electrode of a transistor, said etching process comprised of at least a timed etch process and an endpoint etch process.

Abstract: Various methods of fabricating a conductor structure are provided. In one aspect, a method of fabricating a conductor structure on a first workpiece is provided. A silicon film is formed on the first workpiece. An anti-reflective coating is formed on the silicon film. A mask is formed on a first portion of the anti-reflective coating, while a second portion thereof is left unmasked. The second portion of the anti-reflective coating and the silicon film are etched. The mask is removed, and the anti-reflective coating is removed by isotropic plasma etching. Use of isotropic etching for anti-reflective coating removal eliminates thermal shock associated with heated acid bath anti-reflective coating removal.

Abstract: A method for controlling spacer width in a semiconductor device is provided. A substrate having a gate formed thereon is provided. An insulative layer is formed over at least a portion of the substrate. The insulative layer covers the gate. The thickness of the insulative layer is measured. A portion of the insulative layer to be removed is determined based on the measured thickness of the insulative layer. The portion of the insulative layer is removed to define a spacer on the gate. A processing line for forming a spacer on a gate disposed on a substrate includes a deposition tool, a thickness metrology tool, and automatic process controller, and a spacer etch tool. The deposition tool is adapted to form an insulative layer over at least a portion of the substrate. The insulative layer covers the gate. The thickness metrology tool is adapted to measure the thickness of the insulative layer.

Abstract: Various methods of fabricating a circuit structure, such as a gate electrode or a resistor are provided. In one aspect, a method of fabricating a circuit structure is provided that includes forming a silicon structure on a substrate and forming an oxide film on the silicon structure. A first portion of the oxide film is masked while a second portion is left unmasked. The second portion of the oxide film is removed by isotropic plasma etching to expose a portion of the silicon structure, and the first portion of the oxide film is unmasked. Use of isotropic etching for removal of a resistor protect oxide reduces the potential for isolation structure damage due to aggressive overetching associated with conventional anisotropic etching techniques.

Abstract: The present invention provides for a method and an apparatus for controlling critical dimensions. At least one run of semiconductor devices is processed. A critical dimension measurement is performed upon at least one of the processed semiconductor device. An analysis of the critical dimension measurement is performed. A secondary process upon the semiconductor device in response to the critical dimension analysis is performed.

Abstract: A method for controlling spacer width in a semiconductor device is provided. A substrate having a gate formed thereon is provided. An insulative layer is formed over at least a portion of the substrate. The insulative layer covers the gate. The thickness of the insulative layer is measured. A portion of the insulative layer to be removed is determined based on the measured thickness of the insulative layer. The portion of the insulative layer is removed to define a spacer on the gate. A processing line for forming a spacer on a gate disposed on a substrate includes a deposition tool, a thickness metrology tool, and automatic process controller, and a spacer etch tool. The deposition tool is adapted to form an insulative layer over at least a portion of the substrate. The insulative layer covers the gate. The thickness metrology tool is adapted to measure the thickness of the insulative layer.