Abstract: Systems and techniques for line diagnostics. In particular, disclosed herein are systems and techniques for line diagnostics that sense a state of an electrical cable by using multiple, time-spaced stimuli and detecting their signal reflection time at different threshold levels. Information derived from multiple reflections may be used to determine cable characteristics (e.g., “wire short,” “wire open,” “correctly terminated,” etc.). The systems and techniques disclosed herein may advantageously require less complex hardware and implementation algorithms than conventional time domain reflectometry (TDR) approaches, and thus may be implemented in settings in which TDR was previously unsuitable. Further, if a cable issue is detected, the systems and techniques disclosed herein may determine the approximate location of the cable issue along the cable, accelerating correction of the issue.

Abstract: In safety-critical computer systems, fault tolerance is an important design requirement. Data buses for on-chip interconnection in these processor-based systems are exposed to risk arising from faults in the interconnect itself or in any of the connected peripherals. To provide sufficient fault tolerance, a safety node is inserted between an upstream master section and a downstream slave section of an on-chip bus hierarchy or network. The safety node provides a programmable timeout monitor for detecting a timeout condition for a transaction. If timeout has occurred, the safety node transmits a dummy response back to the master, assumes the role of a master, and waits for the slave device to respond. Furthermore, the safety node rejects any subsequent requests by any of the masters on the upstream section by transmitting a dummy response to those subsequent requests, thus enabling these masters to avoid deadlock or stall.

Abstract: In safety-critical computer systems, fault tolerance is an important design requirement. Data buses for on-chip interconnection in these processor-based systems are exposed to risk arising from faults in the interconnect itself or in any of the connected peripherals. To provide sufficient fault tolerance, a safety node is inserted between an upstream master section and a downstream slave section of an on-chip bus hierarchy or network. The safety node provides a programmable timeout monitor for detecting a timeout condition for a transaction. If timeout has occurred, the safety node transmits a dummy response back to the master, assumes the role of a master, and waits for the slave device to respond. Furthermore, the safety node rejects any subsequent requests by any of the masters on the upstream section by transmitting a dummy response to those subsequent requests, thus enabling these masters to avoid deadlock or stall.