Patents by Inventor Matthew R. Dickie

Matthew R. Dickie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240102167
    Abstract: A boat used in a chemical vapor deposition (CVD) furnace is configured to hold one or more complex three-dimensional (3D) structures when performing a coating. A platform wafer is placed horizontally in the boat to support the complex 3D structures and a mount is positioned to secure the complex 3D structures on the platform wafer during the CVD process. One or more “witness” wafers may also be placed in the boat for analyzing the thin-film coating. The platform wafer may be positioned between or bracketed by the vertical wafers. Parts with coatings manufactured using LPCVD are further disclosed.
    Type: Application
    Filed: September 28, 2023
    Publication date: March 28, 2024
    Applicant: California Institute of Technology
    Inventors: Matthew R. Dickie, Su C. Chi, Billy Chun-Yip Li, William C. West, Harold Frank Greer
  • Patent number: 10384810
    Abstract: Micro-emitter arrays and methods of microfabricating such emitter arrays are provided. The microfabricated emitter arrays incorporate a plurality of emitters with heights greater than 280 microns with uniformity of +/?10 microns arranged on a supporting silicon substrate, each emitter comprising an elongated body extending from the top surface of the substrate and incorporating at least one emitter tip on the distal end of the elongated body thereof. The emitters may be disposed on the substrate in an ordered array in an X by Y grid pattern, wherein X and Y can be any number greater than zero. The micro-emitter arrays may utilize a LMIS propellant source including, for example, gallium, indium, bismuth, or tin. The substrate may incorporate at least one through-via providing a fluid pathway for the LMIS propellant to flow from a propellant reservoir beneath the substrate to the top substrate surface whereupon the micro-emitter array is disposed.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: August 20, 2019
    Assignee: California Institute of Technology
    Inventors: Cecile Jung-Kubiak, Colleen M. Marrese-Reading, Victor E. White, Daniel W. Wilson, Matthew R. Dickie, Karl Y. Yee, Richard E. Muller, James E. Polk, John R. Anderson, Nima Rouhi, Frank Greer
  • Publication number: 20180201395
    Abstract: Micro-emitter arrays and methods of microfabricating such emitter arrays are provided. The microfabricated emitter arrays incorporate a plurality of emitters with heights greater than 280 microns with uniformity of +/?10 microns arranged on a supporting silicon substrate, each emitter comprising an elongated body extending from the top surface of the substrate and incorporating at least one emitter tip on the distal end of the elongated body thereof. The emitters may be disposed on the substrate in an ordered array in an X by Y grid pattern, wherein X and Y can be any number greater than zero. The micro-emitter arrays may utilize a LMIS propellant source including, for example, gallium, indium, bismuth, or tin. The substrate may incorporate at least one through-via providing a fluid pathway for the LMIS propellant to flow from a propellant reservoir beneath the substrate to the top substrate surface whereupon the micro-emitter array is disposed.
    Type: Application
    Filed: July 15, 2015
    Publication date: July 19, 2018
    Applicant: California Institute of Technology
    Inventors: Cecile Jung-Kubiak, Colleen M. Marrese-Reading, Victor E. White, Daniel W. Wilson, Matthew R. Dickie, Karl Y. Yee, Richard E. Muller, James E. Polk, John R. Anderson, Nima Rouhi, Frank Greer
  • Patent number: 9105548
    Abstract: A method and device for imaging or detecting electromagnetic radiation is provided. A device structure includes a first chip interconnected with a second chip. The first chip includes a detector array, wherein the detector array comprises a plurality of light sensors and one or more transistors. The second chip includes a Read Out Integrated Circuit (ROIC) that reads out, via the transistors, a signal produced by the light sensors. A number of interconnects between the ROIC and the detector array can be less than one per light sensor or pixel.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: August 11, 2015
    Assignee: California Institute of Technology
    Inventors: Thomas J. Cunningham, Bruce R. Hancock, Chao Sun, Todd J. Jones, Matthew R. Dickie, Shouleh Nikzad, Michael E. Hoenk, Christopher J. Wrigley, Kenneth W. Newton, Bedabrata Pain
  • Publication number: 20130175430
    Abstract: A method and device for imaging or detecting electromagnetic radiation is provided. A device structure includes a first chip interconnected with a second chip. The first chip includes a detector array, wherein the detector array comprises a plurality of light sensors and one or more transistors. The second chip includes a Read Out Integrated Circuit (ROIC) that reads out, via the transistors, a signal produced by the light sensors. A number of interconnects between the ROIC and the detector array can be less than one per light sensor or pixel.
    Type: Application
    Filed: June 22, 2012
    Publication date: July 11, 2013
    Applicant: CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventors: Thomas J. Cunningham, Bruce R. Hancock, Chao Sun, Todd J. Jones, Matthew R. Dickie, Shouleh Nikzad, Michael E. Hoenk, Christopher J. Wrigley, Kenneth W. Newton, Bedabrata Pain
  • Patent number: 8163094
    Abstract: A process for removing indium oxide from indium bumps in a flip-chip structure to reduce contact resistance, by a multi-step plasma treatment. A first plasma treatment of the indium bumps with an argon, methane and hydrogen plasma reduces indium oxide, and a second plasma treatment with an argon and hydrogen plasma removes residual organics. The multi-step plasma process for removing indium oxide from the indium bumps is more effective in reducing the oxide, and yet does not require the use of halogens, does not change the bump morphology, does not attack the bond pad material or under-bump metallization layers, and creates no new mechanisms for open circuits.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: April 24, 2012
    Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
    Inventors: H. Frank Greer, Todd J. Jones, Richard P. Vasquez, Michael E. Hoenk, Matthew R. Dickie, Shouleh Nikzad
  • Publication number: 20110169160
    Abstract: A method, apparatus, system, and device provide the ability to form one or more solder bumps on one or more materials. The solder bumps are reflowed. During the reflowing, the solder bumps are monitored in real time. The reflow is controlled in real time, thereby controlling a morphology of each of the solder bumps. Further, the wetting of the solder bumps to a surface of the materials is controlled in real time.
    Type: Application
    Filed: January 13, 2011
    Publication date: July 14, 2011
    Applicant: CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventors: Frank Greer, Todd J. Jones, Shouleh Nikzad, Thomas J. Cunningham, Edward R. Blazejewski, Matthew R. Dickie, Michael E. Hoenk