Abstract: Semiconductor devices are provided. In one example, a semiconductor device includes a Group III-nitride semiconductor structure. The semiconductor device may include a gate contact on the Group III-nitride semiconductor structure. The semiconductor device may include a field plate overlapping the Group III-nitride semiconductor structure. The semiconductor device may include a thermally conductive passivation layer overlapping the gate contact. The thermally conductive passivation layer may be between the field plate and the Group III-nitride semiconductor structure. The thermally conductive passivation layer may contact the Group III-nitride semiconductor structure. The thermally conductive passivation layer may have a thermal conductivity of at least about 80 W/(m·k).

Abstract: Semiconductor devices are provided. In one example, a semiconductor device may include a substrate. The semiconductor device may include an aluminum nitride layer on the substrate. The aluminum nitride layer having a thickness of about 200 nm or greater, such as about 400 nm or greater, such as in a range of 500 nm to 1000 nm. The semiconductor device may include a Group III-nitride semiconductor structure on the aluminum nitride layer.

Abstract: Semiconductor devices are provided. In one example, a semiconductor device includes a substrate. The semiconductor device includes a polarity inverting layer on the substrate. The semiconductor device includes a nitrogen-polar (N-Polar) Group III-nitride semiconductor structure on the polarity inverting layer.

Abstract: A vertical transistor is provided that includes a base structure and a superlattice structure overlying the base structure. The superlattice structure comprises a multichannel ridge having sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge. The vertical transistor also includes a source region that overlies the base structure and is in contact with a first end of the superlattice structure, a floating drain that overlies the base structure and is in contact with a second end of the superlattice structure, and a drain. When the vertical transistor is in an ‘ON’ state, current flows from the source region through the channels of the multichannel ridge to the floating drain, which funnels the current to the drain through at least a portion of the base structure.

Abstract: A vertical transistor is provided that includes a base structure and a superlattice structure overlying the base structure. The superlattice structure comprises a multichannel ridge having sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge. The vertical transistor also includes a source region that overlies the base structure and is in contact with a first end of the superlattice structure, a floating drain that overlies the base structure and is in contact with a second end of the superlattice structure, and a drain. When the vertical transistor is in an ‘ON’ state, current flows from the source region through the channels of the multichannel ridge to the floating drain, which funnels the current to the drain through at least a portion of the base structure.

Abstract: A turbine engine assembly and methods involving a turbine engine assembly are provided. In one method, the turbine engine assembly is received. The turbine engine assembly includes an annular stator vane structure disposed at a first orientation. The stator vane structure is reconfigured with the turbine engine assembly to be disposed at a second orientation.

Abstract: A turbine engine assembly and methods involving a turbine engine assembly are provided. In one method, the turbine engine assembly is received. The turbine engine assembly includes an annular stator vane structure disposed at a first orientation. The stator vane structure is reconfigured with the turbine engine assembly to be disposed at a second orientation.