Abstract: The disclosure relates to technology for an adjustable gain device that includes differential input terminals, differential output terminals, signal processing circuitry, and first and second cross-coupled segments. The first cross-coupled segment is coupled between differential input terminals of the adjustable gain device and a negative input of the signal processing circuitry. The second cross-coupled segment is coupled between differential input terminals of the adjustable gain device and a positive input of the signal processing circuitry. The adjustable gain device has a gain that is adjustable by adjusting values of the first and second cross-coupled segments, while maintaining a substantially consistent frequency response and a substantially consistent input impedance of the adjustable gain device, so long as a specified relationship between values of the first and second cross-coupled segments is kept substantially constant.

Abstract: The disclosure relates to technology for a receiver having a receive signal path including a mixer, a differential fixed gain or variable gain amplifier, and a differential filter. The mixer is configured to receive an RF signal, receive an oscillator signal, and output a differential down converted signal at one of a baseband or intermediate frequency (IF). The amplifier is downstream of the mixer and configured to receive the differential down converted signal from the mixer, apply a gain thereto, and output an amplified differential signal. The filter is downstream of the amplifier and configured filter the amplified differential signal received from the amplifier, and output a filtered differential signal. By locating the differential filter downstream of the differential amplifier within the receive signal path, distortion caused by the mixer is mitigated compared to if the filter were located upstream of the filter.

Abstract: The disclosure relates to technology for a receiver having a receive signal path including a mixer, a differential fixed gain or variable gain amplifier, and a differential filter. The mixer is configured to receive an RF signal, receive an oscillator signal, and output a differential down converted signal at one of a baseband or intermediate frequency (IF). The amplifier is downstream of the mixer and configured to receive the differential down converted signal from the mixer, apply a gain thereto, and output an amplified differential signal. The filter is downstream of the amplifier and configured filter the amplified differential signal received from the amplifier, and output a filtered differential signal. By locating the differential filter downstream of the differential amplifier within the receive signal path, distortion caused by the mixer is mitigated compared to if the filter were located upstream of the filter.

Abstract: The disclosure relates to technology for an adjustable gain device that includes differential input terminals, differential output terminals, signal processing circuitry, and first and second cross-coupled segments. The first cross-coupled segment is coupled between differential input terminals of the adjustable gain device and a negative input of the signal processing circuitry. The second cross-coupled segment is coupled between differential input terminals of the adjustable gain device and a positive input of the signal processing circuitry. The adjustable gain device has a gain that is adjustable by adjusting values of the first and second cross-coupled segments, while maintaining a substantially consistent frequency response and a substantially consistent input impedance of the adjustable gain device, so long as a specified relationship between values of the first and second cross-coupled segments is kept substantially constant.

Abstract: The disclosure relates to technology for a fully differential adjustable gain device that includes differential input terminals, differential output terminals, fully differential signal processing circuitry, and first and second cross-coupled segments. The first cross-coupled segment is coupled between differential input terminals of the fully differential adjustable gain device and a negative input of the fully differential signal processing circuitry. The second cross-coupled segment is coupled between differential input terminals of the fully differential adjustable gain device and a positive input of the fully differential signal processing circuitry.

Abstract: Each program thread running on a computing device has an associated data stack and control stack. A stack displacement value is generated, which is the difference between the memory address of the base of the data stack and the memory address of the base of the control stack, and is stored in a register of a processor of the computing device that is restricted to operating system kernel use. For each thread on which return flow guard is enabled, prologue and epilogue code is added to each function of the thread (e.g., by a memory manager of the computing device). The data stack and the control stack each store a return address for the function, and when the function completes the epilogue code allows the function to return only if the return addresses on the data stack and the control stack match.

Abstract: Each program thread running on a computing device has an associated data stack and control stack. A stack displacement value is generated, which is the difference between the memory address of the base of the data stack and the memory address of the base of the control stack, and is stored in a register of a processor of the computing device that is restricted to operating system kernel use. For each thread on which return flow guard is enabled, prologue and epilogue code is added to each function of the thread (e.g., by a memory manager of the computing device). The data stack and the control stack each store a return address for the function, and when the function completes the epilogue code allows the function to return only if the return addresses on the data stack and the control stack match.

Abstract: In response to a memory allocation request received from an application thread, a random number is obtained (e.g., from a random number list previously populated with multiple random numbers). A starting location in at least a portion of a bitmap associated with a region including multiple blocks of the memory is determined based on the random number. A portion of the bitmap is scanned, beginning at the starting location, to identify a location in the bitmap corresponding to an available block of the multiple blocks, and an indication of this available block is returned to the application thread.

Abstract: A system on a chip (SoC) or other integrated system can include a first processor and at least one additional processor sharing a page table. The shared page table can include permission bits including a first permission indicator supporting the processor and a second permission indicator supporting at least one of the at least one additional processor. In one implementation, that page table can include at least one additional bit to accommodate encodings that support the at least one additional processor. When one of the processors accesses memory, a method is performed in which a shared page table is accessed and a value of the permission indicator(s) is read from the page table to determine permissions for performing certain actions including executing a page; read/write of the page; or kernel mode with respect to the page.

Abstract: In response to a memory allocation request received from an application thread, a random number is obtained (e.g., from a random number list previously populated with multiple random numbers). A starting location in at least a portion of a bitmap associated with a region including multiple blocks of the memory is determined based on the random number. A portion of the bitmap is scanned, beginning at the starting location, to identify a location in the bitmap corresponding to an available block of the multiple blocks, and an indication of this available block is returned to the application thread.

Abstract: The subject disclosure is directed towards preventing the exploitation by malicious code of object state corruption vulnerabilities, such as use-after-free vulnerabilities. An object class is configured with a secret cookie in a virtual function table of the object, e.g., inserted at compile time. An instrumentation check inserted in the program code evaluates the secret cookie to determine whether the object state has been corrupted before object access (e.g., a call to one of the object's methods) is allowed. If corrupted, access to the object is prevented by the instrumentation check. Another instrumentation check may be used to determine whether the object's virtual table pointer points to a location outside of the module that contains the legitimate virtual function table; if so, object access is prevented.

Abstract: In response to a memory allocation request received from an application thread, a random number is obtained (e.g., from a random number list previously populated with multiple random numbers). A starting location in at least a portion of a bitmap associated with a region including multiple blocks of the memory is determined based on the random number. A portion of the bitmap is scanned, beginning at the starting location, to identify a location in the bitmap corresponding to an available block of the multiple blocks, and an indication of this available block is returned to the application thread.

Abstract: In response to a memory allocation request received from an application thread, a random number is obtained (e.g., from a random number list previously populated with multiple random numbers). A starting location in at least a portion of a bitmap associated with a region including multiple blocks of the memory is determined based on the random number. A portion of the bitmap is scanned, beginning at the starting location, to identify a location in the bitmap corresponding to an available block of the multiple blocks, and an indication of this available block is returned to the application thread.

Abstract: The subject disclosure is directed towards preventing the exploitation by malicious code of object state corruption vulnerabilities, such as use-after-free vulnerabilities. An object class is configured with a secret cookie in a virtual function table of the object, e.g., inserted at compile time. An instrumentation check inserted in the program code evaluates the secret cookie to determine whether the object state has been corrupted before object access (e.g., a call to one of the object's methods) is allowed. If corrupted, access to the object is prevented by the instrumentation check. Another instrumentation check may be used to determine whether the object's virtual table pointer points to a location outside of the module that contains the legitimate virtual function table; if so, object access is prevented.

Abstract: An analogue-to-digital converter apparatus comprises a first integrator coupled to a second integrator. The first and second integrators are coupled so as to provide a complex pole. The first integrator is selectively electrically decoupleable from the second integrator, thereby removing the complex pole.

Abstract: A switching amplifier drives a load or audio transducer. A digital integral noise shaping circuit converts a digital input such as audio content to an output digital pulse width modulated signal using an integrator. The integrator integrates the digital input, a variable frequency reference pulse width modulated signal and an inverse of the output digital pulse width modulated signal. A half bridge amplifier receives the output digital pulse width modulated signal and drives the load or audio transducer. A variable frequency generator generates the variable frequency reference pulse width modulated signal with an approximately equal duty ratio or alternatively varies the variable frequency pulse width modulated signal above and below about a fifty percent duty ratio.

Abstract: A switching amplifier drives a load or audio transducer. A digital integral noise shaping circuit converts a digital input such as audio content to an output digital pulse width modulated signal using an integrator. The integrator integrates the digital input, a variable frequency reference pulse width modulated signal and an inverse of the output digital pulse width modulated signal. A half bridge amplifier receives the output digital pulse width modulated signal and drives the load or audio transducer. A variable frequency generator generates the variable frequency reference pulse width modulated signal with an approximately equal duty ratio or alternatively varies the variable frequency pulse width modulated signal above and below about a fifty percent duty ratio.

Abstract: An analogue-to-digital converter apparatus comprises a first integrator coupled to a second integrator. The first and second integrators are coupled so as to provide a complex pole. The first integrator is selectively electrically decoupleable from the second integrator, thereby removing the complex pole.

Abstract: An RF modulator supporting wide-band signals includes IQ modulation by interleaving the in-phase and quadrature signals. The modulator can be implemented using an integrated circuit having a baseband in-phase stage that receives an in-phase analog input signal, a baseband quadrature stage that receives a quadrature analog input signal, and a switching mixer having a plurality of switches. The switching mixer receives in-phase and quadrature signals from the baseband in-phase stage and the baseband quadrature stage. The switching mixer produces a differential signal combining the in-phase and quadrature signals by interleaving the signals over a plurality of phases of a carrier period.

Abstract: A circuit (104, 106) includes a comparison circuit (202, 504, 506, 602) and a correction circuit (204, 508, 510, 604). The comparison circuit provides a comparison signal (212, 524, 526, 612) in response to an error value (210, 520, 522, 610) and a reference value (214). The error value is based on a pulse modulated input signal (114) and a pulse modulated output signal (118). The correction circuit asynchronously provides a corrected pulse modulated signal (116) by selectively delaying and advancing an edge of the pulse modulated input signal based on the comparison signal. The pulse modulated output signal is based on the corrected pulse modulated signal.