Patents by Inventor Matthew R. Wordeman
Matthew R. Wordeman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10839935Abstract: A dynamic redundancy memory includes a redundancy control module and an ECC module. The ECC detects bit errors, stores the addresses of the error bits, counts the bit errors. If the number of errors exceeds a threshold, the ECC identifies the address as a suspect bit and sends a suspect bit signal to the redundancy control module, which determines whether the suspect bit address is already stored in a redundancy element. If already stored, the element is marked bad, the address of the suspect bit is replaced with a new redundant address and the suspect bit address is stored in a good unused element. The ECC determines whether the error occurrences at the address exceeds a bit error rate threshold. If the error rate threshold is exceeded, the ECC identifies the address as suspect bit and sends the suspect bit signal to the redundancy control module.Type: GrantFiled: February 5, 2019Date of Patent: November 17, 2020Assignee: International Business Machines CorporationInventors: Daniel Worledge, John K. DeBrosse, Kotb Jabeur, Matthew R. Wordeman
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Publication number: 20200250029Abstract: A dynamic redundancy memory includes a redundancy control module and an ECC module. The ECC detects bit errors, stores the addresses of the error bits, counts the bit errors. If the number of errors exceeds a threshold, the ECC identifies the address as a suspect bit and sends a suspect bit signal to the redundancy control module, which determines whether the suspect bit address is already stored in a redundancy element. If already stored, the element is marked bad, the address of the suspect bit is replaced with a new redundant address and the suspect bit address is stored in a good unused element. The ECC determines whether the error occurrences at the address exceeds a bit error rate threshold. If the error rate threshold is exceeded, the ECC identifies the address as suspect bit and sends the suspect bit signal to the redundancy control module.Type: ApplicationFiled: February 5, 2019Publication date: August 6, 2020Inventors: Daniel Worledge, John K. DeBrosse, Kotb Jabeur, Matthew R. Wordeman
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Patent number: 10726897Abstract: A magnetoresistive random access memory (MRAM) system is described. The system includes a sense amplifier circuit for sensing a data state of an MRAM data cell. The circuit includes a first leg and a second leg, and is configured to perform a two-phase read including a first phase in which a first transistor is coupled to a reference resistance circuitry and a second transistor is coupled to a data resistance circuitry, and a second phase in which the first transistor is coupled to the data resistance circuitry and the second transistor is coupled to the reference resistance circuitry. The circuit further includes a reference trim circuitry and a data trim circuitry configured to correct for device mismatch errors relating to the two-phase read of the sense amplifier circuit. The circuit further includes a comparator circuit configured to output the data state of the data cell.Type: GrantFiled: May 14, 2019Date of Patent: July 28, 2020Assignee: International Business Machines CorporationInventors: Thomas Martin Maffitt, John Kenneth Debrosse, Matthew R Wordeman
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Patent number: 9799386Abstract: Improved STT MRAM midpoint reference cell configurations are provided. In one aspect, a STT MRAM midpoint reference cell includes: a plurality of word lines having at least one write reference word line and at least one read reference word line; a plurality of bit lines perpendicular to the word lines; at least one source line perpendicular to the bit lines; at least one first magnetic tunnel junction in series with i) a first field effect transistor gated by the write reference word line and ii) a second field effect transistor gated by the read reference word line; and at least one second magnetic tunnel junction in series with iii) a third field effect transistor gated by the write reference word line and iv) a fourth field effect transistor gated by the read reference word line. A method of operating a STT MRAM midpoint reference cell is also provided.Type: GrantFiled: August 30, 2016Date of Patent: October 24, 2017Assignee: International Business Machines CorporationInventors: John K. DeBrosse, Matthew R. Wordeman
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Patent number: 8928350Abstract: There is provided a strata manager within a 3D chip stack having two or more strata. The strata manager includes a plurality of scannable configuration registers, each being arranged on a respective one of the two or more strata for storing a set of bits. The set of bits is configured to program an operation of a corresponding one of the two or more strata on which the set of bits is stored or a device thereon. Additionally, a stratum identifier within a 3D stack and stack-wide scan circuit within a 3D stack are provided.Type: GrantFiled: September 7, 2012Date of Patent: January 6, 2015Assignee: International Business Machines CorporationInventors: Liang-Teck Pang, Joel A. Silberman, Matthew R. Wordeman
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Patent number: 8828800Abstract: An array of contact pads on a semiconductor structure has a pitch less than twice an overlay tolerance of a bonding process employed to vertically stack semiconductor structures. A set of contact pads within the area of overlay variation for a matching contact pin may be electrically connected to an array of programmable contacts such that one programmable contact is connected to each contact pad within the area of overlay variation. One contact pad may be provided with a plurality of programmable contacts. The variability of contacts between contact pins and contact pads is accommodated by connecting or disconnecting programmable contacts after the stacking of semiconductor structures. Since the pitch of the array of contact pins may be less than twice the overlay variation of the bonding process, a high density of interconnections is provided in the vertically stacked structure.Type: GrantFiled: March 12, 2012Date of Patent: September 9, 2014Assignee: International Business Machines CorporationInventors: Leland Chang, Matthew R. Wordeman, Albert M. Young
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Patent number: 8586957Abstract: A three-terminal switching device for use in integrated circuit devices, including a phase change material (PCM) disposed in contact between a first terminal and a second terminal; a heating device disposed in direct electrical contact between said second terminal and a third terminal, said heating device positioned proximate said PCM, and configured to switch the conductivity of a transformable portion of said PCM between a lower resistance crystalline state and a higher resistance amorphous state; and an insulating layer configured to electrically isolate said heater from said PCM material, and said heater from said first terminal.Type: GrantFiled: September 1, 2009Date of Patent: November 19, 2013Assignee: International Business Machines CorporationInventors: Lia Krusin-Elbaum, Dennis M. Newns, Matthew R. Wordeman
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Patent number: 8570088Abstract: There is provided a synchronization circuit for a 3D chip stack having multiple circuits and multiple strata interconnected using a first and a second stack-wide broadcast connection chain. The synchronization circuit includes the following, on each stratum. A synchronizer connected to the first connection chain receives an asynchronous signal therefrom and performs a synchronization to provide a synchronous signal. A driver is connected to the second chain for driving the synchronous signal. A latch connected to the second chain receives the synchronous signal driven by the driver on a same or different stratum within a next clock cycle from the synchronization to provide the stack-wide synchronous signal to a circuit on a same stratum. An output of a single driver on one stratum is selected at any given time for use by the latch on all strata.Type: GrantFiled: April 25, 2013Date of Patent: October 29, 2013Assignee: International Business Machines CorporationInventors: Joel A. Silberman, Matthew R. Wordeman
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Patent number: 8519735Abstract: There is provided a strata manager within a 3D chip stack having two or more strata. The strata manager includes a plurality of scannable configuration registers, each being arranged on a respective one of the two or more strata for storing a set of bits. The set of bits is configured to program an operation of a corresponding one of the two or more strata on which the set of bits is stored or a device thereon. Additionally, a stratum identifier within a 3D stack and stack-wide scan circuit within a 3D stack are provided.Type: GrantFiled: August 25, 2011Date of Patent: August 27, 2013Assignee: International Business Machines CorporationInventors: Liang-Teck Pang, Joel A. Silberman, Matthew R. Wordeman
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Patent number: 8476953Abstract: There is provided a synchronization circuit for a 3D chip stack having multiple circuits and multiple strata interconnected using a first and a second stack-wide broadcast connection chain. The synchronization circuit includes the following, on each stratum. A synchronizer connected to the first connection chain receives an asynchronous signal therefrom and performs a synchronization to provide a synchronous signal. A driver is connected to the second chain for driving the synchronous signal. A latch connected to the second chain receives the synchronous signal driven by the driver on a same or different stratum within a next clock cycle from the synchronization to provide the stack-wide synchronous signal to a circuit on a same stratum. An output of a single driver on one stratum is selected at any given time for use by the latch on all strata.Type: GrantFiled: August 25, 2011Date of Patent: July 2, 2013Assignee: International Business Machines CorporationInventors: Joel A. Silberman, Matthew R. Wordeman
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Patent number: 8476771Abstract: There is provided a connection configuration for a multiple layer chip stack having two or more strata. Each of the two or more strata has multiple circuit components, a front-side and a back-side. The connection configuration includes a connection pair having as members a front-side connection and a backside connection unconnected to the front-side connection. The front-side connection and the backside connection are co-located with respect to each other on a given stratum from among the two or more strata, and are respectively connected to different ones of the multiple circuit components on the given stratum. At least one of the front-side connection and the backside connection is also connected to a particular one of the multiple circuit components on an adjacent stratum to the given stratum from among the two or more strata.Type: GrantFiled: August 25, 2011Date of Patent: July 2, 2013Assignee: International Business Machines CorporationInventors: Michael R. Scheuermann, Joel A. Silberman, Matthew R. Wordeman
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Patent number: 8466444Abstract: A switching circuit includes a plurality of three-terminal PCM switching devices connected between a voltage supply terminal and a sub-block of logic. Each of the switching devices includes a PCM disposed in contact between a first terminal and a second terminal, a heating device disposed in contact between the second terminal and a third terminal, the heating device positioned proximate the PCM, and configured to switch the conductivity of a transformable portion of the PCM between a lower resistance state and a higher resistance state; and an insulating layer configured to electrically isolate the heater from said PCM material, and the heater from the first terminal. The third terminal of a first of the PCM switching devices is coupled to a set/reset switch, and the third terminal of the remaining PCM switching devices is coupled to the second terminal of an adjacent PCM switching device in a cascade configuration.Type: GrantFiled: February 27, 2012Date of Patent: June 18, 2013Assignee: International Business Machines CorporationInventors: Lia Krusin-Elbaum, Dennis M. Newns, Matthew R. Wordeman
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Publication number: 20130055183Abstract: There is provided a method for verifying inter-stratum connectivity for two or more strata to be combined into a 3D chip stack. Each of the two or more strata has 3D elements including active 3D elements, mechanical 3D elements, and dummy 3D elements. The method includes performing a respective 2D layout versus schematic verification on each of the two or more strata with respect to at least the 3D elements to pre-ensure an absence of shorts between the 3D elements when the two or more strata are subsequently stacked into the 3D chip stack. The method further includes checking inter-stratum interconnectivity between each adjacent pair of strata in the 3D chip stack.Type: ApplicationFiled: August 25, 2011Publication date: February 28, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: MICHAEL P. BEAKES, SHIH-HSIEN LO, MICHAEL R. SCHEUERMANN, MATTHEW R. WORDEMAN
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Publication number: 20130049213Abstract: There is provided a connection configuration for a multiple layer chip stack having two or more strata. Each of the two or more strata has multiple circuit components, a front-side and a back-side. The connection configuration includes a connection pair having as members a front-side connection and a backside connection unconnected to the front-side connection. The front-side connection and the backside connection are co-located with respect to each other on a given stratum from among the two or more strata, and are respectively connected to different ones of the multiple circuit components on the given stratum. At least one of the front-side connection and the backside connection is also connected to a particular one of the multiple circuit components on an adjacent stratum to the given stratum from among the two or more strata.Type: ApplicationFiled: August 25, 2011Publication date: February 28, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: MICHAEL R. SCHEUERMANN, JOEL A. SILBERMAN, MATTHEW R. WORDEMAN
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Publication number: 20130049825Abstract: There is provided a synchronization circuit for a 3D chip stack having multiple circuits and multiple strata interconnected using a first and a second stack-wide broadcast connection chain. The synchronization circuit includes the following, on each stratum. A synchronizer connected to the first connection chain receives an asynchronous signal therefrom and performs a synchronization to provide a synchronous signal. A driver is connected to the second chain for driving the synchronous signal. A latch connected to the second chain receives the synchronous signal driven by the driver on a same or different stratum within a next clock cycle from the synchronization to provide the stack-wide synchronous signal to a circuit on a same stratum. An output of a single driver on one stratum is selected at any given time for use by the latch on all strata.Type: ApplicationFiled: August 25, 2011Publication date: February 28, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joel A. Silberman, Matthew R. Wordeman
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Publication number: 20130049796Abstract: There is provided a strata manager within a 3D chip stack having two or more strata. The strata manager includes a plurality of scannable configuration registers, each being arranged on a respective one of the two or more strata for storing a set of bits. The set of bits is configured to program an operation of a corresponding one of the two or more strata on which the set of bits is stored or a device thereon. Additionally, a stratum identifier within a 3D stack and stack-wide scan circuit within a 3D stack are provided.Type: ApplicationFiled: September 7, 2012Publication date: February 28, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: LIANG-TECK PANG, JOEL A. SILBERMAN, MATTHEW R. WORDEMAN
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Publication number: 20130049795Abstract: There is provided a strata manager within a 3D chip stack having two or more strata. The strata manager includes a plurality of scannable configuration registers, each being arranged on a respective one of the two or more strata for storing a set of bits. The set of bits is configured to program an operation of a corresponding one of the two or more strata on which the set of bits is stored or a device thereon. Additionally, a stratum identifier within a 3D stack and stack-wide scan circuit within a 3D stack are provided.Type: ApplicationFiled: August 25, 2011Publication date: February 28, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: LIANG-TECK PANG, JOEL A. SILBERMAN, MATTHEW R. WORDEMAN
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Patent number: 8381156Abstract: There is provided a method for verifying inter-stratum connectivity for two or more strata to be combined into a 3D chip stack. Each of the two or more strata has 3D elements including active 3D elements, mechanical 3D elements, and dummy 3D elements. The method includes performing a respective 2D layout versus schematic verification on each of the two or more strata with respect to at least the 3D elements to pre-ensure an absence of shorts between the 3D elements when the two or more strata are subsequently stacked into the 3D chip stack. The method further includes checking inter-stratum interconnectivity between each adjacent pair of strata in the 3D chip stack.Type: GrantFiled: August 25, 2011Date of Patent: February 19, 2013Assignee: International Business Machines CorporationInventors: Michael P. Beakes, Shih-Hsien Lo, Michael R. Scheuermann, Matthew R. Wordeman
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Publication number: 20120171819Abstract: An array of contact pads on a semiconductor structure has a pitch less than twice an overlay tolerance of a bonding process employed to vertically stack semiconductor structures. A set of contact pads within the area of overlay variation for a matching contact pin may be electrically connected to an array of programmable contacts such that one programmable contact is connected to each contact pad within the area of overlay variation. One contact pad may be provided with a plurality of programmable contacts. The variability of contacts between contact pins and contact pads is accommodated by connecting or disconnecting programmable contacts after the stacking of semiconductor structures. Since the pitch of the array of contact pins may be less than twice the overlay variation of the bonding process, a high density of interconnections is provided in the vertically stacked structure.Type: ApplicationFiled: March 12, 2012Publication date: July 5, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Leland Chang, Matthew R. Wordeman, Albert M. Young
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Publication number: 20120153248Abstract: A switching circuit includes a plurality of three-terminal PCM switching devices connected between a voltage supply terminal and a sub-block of logic. Each of the switching devices includes a PCM disposed in contact between a first terminal and a second terminal, a heating device disposed in contact between the second terminal and a third terminal, the heating device positioned proximate the PCM, and configured to switch the conductivity of a transformable portion of the PCM between a lower resistance state and a higher resistance state; and an insulating layer configured to electrically isolate the heater from said PCM material, and the heater from the first terminal. The third terminal of a first of the PCM switching devices is coupled to a set/reset switch, and the third terminal of the remaining PCM switching devices is coupled to the second terminal of an adjacent PCM switching device in a cascade configuration.Type: ApplicationFiled: February 27, 2012Publication date: June 21, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lia Krusin-Elbaum, Dennis M. Newns, Matthew R. Wordeman