Abstract: Apparatuses, systems, and methods for controlling cache allocations in a configurable combined private and shared cache in a processor-based system. The processor-based system is configured to receive a cache allocation request to allocate a line in a share cache structure, which may further include a client identification (ID). The cache allocation request and the client ID can be compared to a sub-non-uniform memory access (NUMA) (sub-NUMA) bit mask and a client allocation bit mask to generate a cache allocation vector. The sub-NUMA bit mask may have been programmed to indicate that processing cores associated with a sub-NUMA region are available, whereas processing cores associated with other sub-NUMA regions are not available, and the client allocation bit mask may have been programmed to indicate that processing cores are available.

Abstract: Aspects disclosed in the detailed description include configuring a configurable combined private and shared cache in a processor. Related processor-based systems and methods are also disclosed. A combined private and shared cache structure is configurable to select a private cache portion and a shared cache portion.

Abstract: The system or device may build one or more data packets by dividing a given payload for a packet into data blocks and inserting data checks for each data block sequentially into the packet payload. The device may generate, for each of the data blocks, a corresponding data check block corresponding to data in each data block. The device may send or arrange the data blocks and the corresponding data check blocks such that each of the data blocks is followed by the corresponding error check block in the packet. Using the corresponding check block, each of the data blocks is independently verifiable, so that the data blocks may be used upon receipt, even if the payload is not completely received.

Abstract: Address range memory mirroring in a computer system, and related methods and computer-readable media. The computer system includes one or more memory mirror agents that are each configured to be programmed to mirror write data of a write request to a memory address mapped to the memory mirror agent. The memory mirror agent is configured to mirror write data to a redundant memory space in memory if the write memory address is within a programmed memory space to be mirrored by the memory mirror agent. The memory mirror agent can be programmed to perform memory mirroring based on specific address ranges to provide flexibility in controlling and changing the exact memory space of the memory system to be mirrored. If an error is detected in read data in response to a memory read request, the memory mirror agent can retrieve the stored redundant data to maintain data integrity.

Abstract: The system or device may build one or more data packets by dividing a given payload for a packet into data blocks and inserting data checks for each data block sequentially into the packet payload. The device may generate, for each of the data blocks, a corresponding data check block corresponding to data in each data block. The device may send or arrange the data blocks and the corresponding data check blocks such that each of the data blocks is followed by the corresponding error check block in the packet. Using the corresponding check block, each of the data blocks is independently verifiable, so that the data blocks may be used upon receipt, even if the payload is not completely received.

Abstract: A system-on-a-chip (SoC) with one or more processors and other system components may have one or more peripheral component interconnect express (PCIe) physical connections between the processors and other system components to provide agent-to-agent communication. The agents on the communication fabric of the SoC may transmit data through the hardware PCIe interface where a transmitter device of an agent or digital logic component receives at least one data block for transmission and receives a flag corresponding to the at least one data block. The transmitter device may then send, via a PCIe physical layer, the received data blocks as a payload of a packet based on the flag, where the packet has a PCIe compliant header. The payload of the packet with the PCIe header may be entirely composed of these data blocks or flits from the agent.

Abstract: Apparatuses, systems, and methods for implied sequence numbering of transactions in a processor-based system. The processor-based system includes a transmit circuit configured to generate an implied sequence number for each entry to be transmitted as a packet. The transmit circuit is configured to generate a packet to be transmitted based on an entry, wherein the packet including the payload information and the transmit check value based on the implied sequence number and associated with the entry. In this manner, including an individual sequence number with every transmitted packet may be reduced or avoided to reduce or avoid consuming bandwidth on the communications interface, as the bits used by the sequence number could ordinarily be used for data transmission instead. A receiver circuit is configured to receive the transmitted packet including the payload and the transmit check value, wherein the transmit check value is based on the transmit sequence number.

Abstract: Aspects disclosed in the detailed description include configuring a configurable combined private and shared cache in a processor. Related processor-based systems and methods are also disclosed. A combined private and shared cache structure is configurable to select a private cache portion and a shared cache portion.

Abstract: Apparatuses, systems, and methods for controlling cache allocations in a configurable combined private and shared cache in a processor-based system. The processor-based system is configured to receive a cache allocation request to allocate a line in a share cache structure, which may further include a client identification (ID). The cache allocation request and the client ID can be compared to a sub-non-uniform memory access (NUMA) (sub-NUMA) bit mask and a client allocation bit mask to generate a cache allocation vector. The sub-NUMA bit mask may have been programmed to indicate that processing cores associated with a sub-NUMA region are available, whereas processing cores associated with other sub-NUMA regions are not available, and the client allocation bit mask may have been programmed to indicate that processing cores are available.

Abstract: Apparatuses, systems, and methods for configuring combined private and shared cache levels in a processor-based system. The processor-based system includes a processor that includes a plurality of processing cores each including execution circuits which are coupled to respective cache(s) and a configurable combined private and shared cache, and which may receive instructions and data on which to perform operations from the cache(s) and the combined private and shared cache. A shared cache portion of each configurable combined private and shared cache can be treated as an independently-assignable portion of the overall shared cache, which is effectively the shared cache portions of all of the processing cores. Each independently-assignable portion of the overall shared cache can be associated with a particular client running on the processor as an example. This approach can provide greater granularity of cache partitioning of a shared cache between particular clients running on a processor.

Abstract: The system or device may build one or more data packets by dividing a given payload for a packet into data blocks and inserting data checks for each data block sequentially into the packet payload. The device may generate, for each of the data blocks, a corresponding data check block corresponding to data in each data block. The device may send or arrange the data blocks and the corresponding data check blocks such that each of the data blocks is followed by the corresponding error check block in the packet. Using the corresponding check block, each of the data blocks is independently verifiable, so that the data blocks may be used upon receipt, even if the payload is not completely received.