Abstract: Example implementations relate to storing data in a storage system. An example includes receiving, by a storage controller of a storage system, a data unit to be stored in persistent storage of the storage system. The storage controller determines maximum and minimum entropy values for the received data unit. The storage controller determines, based on at least the minimum entropy value and the maximum entropy value, whether the received data unit is viable for data reduction. In response to a determination that the received data unit is viable for data reduction, The storage controller performs at least one reduction operation on the received data unit.

Abstract: In some examples, a system dynamically adjusts a prefetching load with respect to a prefetch cache based on a measure of past utilizations of the prefetch cache, wherein the prefetching load is to prefetch data from storage into the prefetch cache.

Abstract: In some examples, a system dynamically adjusts a prefetching load with respect to a prefetch cache based on a measure of past utilizations of the prefetch cache, wherein the prefetching load is to prefetch data from storage into the prefetch cache.

Abstract: Systems and methods are provided for lock-free thread scheduling. Threads may be placed in a ring buffer shared by all computer processing units (CPUs), e.g., in a node. A thread assigned to a CPU may be placed in the CPU's local run queue. However, when a CPU's local run queue is cleared, that CPU checks the shared ring buffer to determine if any threads are waiting to run on that CPU, and if so, the CPU pulls a batch of threads related to that ready-to-run thread to execute. If not, an idle CPU randomly selects another CPU to steal threads from, and the idle CPU attempts to dequeue a thread batch associated with the CPU from the shared ring buffer. Polling may be handled through the use of a shared poller array to dynamically distribute polling across multiple CPUs.

Abstract: A process includes, responsive to a first epoch of a sequence of epochs, a plurality of processors accessing first entries of a first buffer that is shared among the plurality of processors. The first entries identify a first subset of hardware devices to be polled of a plurality of hardware devices. Responsive to the accessing, the plurality of processors poll the first subset of hardware devices. Responsive to the first epoch, the process includes, responsive to results of the polling, the plurality of processors updating delay orders that are associated with the first subset of hardware devices; and the plurality of processors adding second entries identifying the first subset of hardware devices to a plurality of second buffers based on the delay orders, where each second buffer of the plurality of second buffers corresponds to a different delay order of the delay orders.

Abstract: A process includes, responsive to a first epoch of a sequence of epochs, a plurality of processors accessing first entries of a first buffer that is shared among the plurality of processors. The first entries identify a first subset of hardware devices to be polled of a plurality of hardware devices. Responsive to the accessing, the plurality of processors poll the first subset of hardware devices. Responsive to the first epoch, the process includes, responsive to results of the polling, the plurality of processors updating delay orders that are associated with the first subset of hardware devices; and the plurality of processors adding second entries identifying the first subset of hardware devices to a plurality of second buffers based on the delay orders, where each second buffer of the plurality of second buffers corresponds to a different delay order of the delay orders.

Abstract: A process includes determining a first degree of throttling to apply to a polling of hardware devices by a hardware processor based on a historical total utilization of the hardware processor; and determining a second degree of throttling to apply to the polling of hardware devices by the hardware processor based on a historical polling utilization of the hardware processor. The hardware processor includes, responsive to an upcoming hardware device polling cycle for the hardware processor and based on the first degree of throttling and the second degree of throttling, regulating whether the hardware processor bypasses the hardware device polling cycle or executes the hardware device polling cycle.

Abstract: In some examples, a system receives a write request from a requester to write first data to a storage system that implements redundancy in which redundancy information is stored for data in the storage system. The system initiates the write to the storage system. The system determines that partial hardening for the first data has been achieved based on detecting that an information portion has been written to the storage system for the write request, the information portion being less than an entirety of the first data and the first parity information. In response to the determining of the partial hardening, the system notifies the requester of completion of the write request.

Abstract: Systems and methods are provided for lock-free thread scheduling. Threads may be placed in a ring buffer shared by all computer processing units (CPUs), e.g., in a node. A thread assigned to a CPU may be placed in the CPU's local run queue. However, when a CPU's local run queue is cleared, that CPU checks the shared ring buffer to determine if any threads are waiting to run on that CPU, and if so, the CPU pulls a batch of threads related to that ready-to-run thread to execute. If not, an idle CPU randomly selects another CPU to steak threads from, and the idle CPU attempts to dequeue a thread batch associated with the CPU from the shared ring buffer. Polling may be handled through the use of a shared poller array to dynamically distribute polling across multiple CPUs.

Abstract: At least one simulated snapshot is created for a parent volume stored on a storage subsystem. A processor updates the at least one simulated snapshot in response to modification operations to the parent volume, wherein the at least one simulated snapshot stores metadata but not any prior version of data that is modified in response to the modification operations to the parent volume. The processor provides information relating to usage of the at least one simulated snapshot based on accessing the metadata of the at least one simulated snapshot.