Patents by Inventor Matthew S. Geuss

Matthew S. Geuss has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11928015
    Abstract: A fault insertion device (FID) comprises a transceiver and an FPGA. The transceiver receives signals from a MIL-STD-1553/1760 communications bus. The FPGA evaluates the signals received from the communications bus against a set of rules stored by the FPGA. Based upon the set of rules, the FPGA can selectively modify messages received from the communications bus prior to transmission to a remote terminal or a bus controller that is configured to communicate on the communications bus.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: March 12, 2024
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Jason P. Krein, Jeremy W. Giron, Matthew S. Geuss, Robert Nevett, IV, Stephen T. Simpson, Roger Martin Kilgore, Jacob Edward Leemaster