Patents by Inventor Matthew S. Grady
Matthew S. Grady has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9336109Abstract: A method of testing a device is disclosed. Test data is obtained for a device testing program that tests the device. An adaptation command for testing the device is determined at an adaptive testing engine using obtained test data. The adaptation command is sent from the adaptive testing engine to a tool control application. The tool control application uses the adaptation command to control an operation related to the testing of the device.Type: GrantFiled: February 26, 2013Date of Patent: May 10, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David E. Atkinson, Matthew S. Grady, Donald L. LaCroix, David B. Lutton, II, Bradley D. Pepper, Randolph P. Steel
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Patent number: 9311201Abstract: A method of testing a device is disclosed. Test data is obtained for a device testing program that tests the device. An adaptation command for testing the device is determined at an adaptive testing engine using obtained test data. The adaptation command is sent from the adaptive testing engine to a tool control application. The tool control application uses the adaptation command to control an operation related to the testing of the device.Type: GrantFiled: August 22, 2012Date of Patent: April 12, 2016Assignee: International Business Machines CorporationInventors: David E. Atkinson, Matthew S. Grady, Donald L. LaCroix, David B. Lutton, II, Bradley D. Pepper, Randolph P. Steel
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Patent number: 8689066Abstract: A method of implementing integrated circuit device testing includes performing baseline testing of a first group of chips using a full set of test patterns, and for chip identified as failing, determining, a score for each test pattern in the full set. The score is indicative of an ability of the test pattern to uniquely identify a failing chip with respect to other test patterns. Following the baseline testing, streamlined testing on a second group of chips is performed, using a reduced set of the test patterns having highest average scores as determined by the baseline testing. Following the streamlined testing, full testing on a third group of chips is performed using the full set of test patterns, and updating the average score for each pattern. Further testing alternates between the streamlined testing and the full testing for additional groups of chips.Type: GrantFiled: June 29, 2011Date of Patent: April 1, 2014Assignee: International Business Machines CorporationInventors: Matthew S. Grady, Mark C. Johnson, Bradley D. Pepper, Dean G. Percy, Joseph C. Pranys
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Publication number: 20140059386Abstract: A method of testing a device is disclosed. Test data is obtained for a device testing program that tests the device. An adaptation command for testing the device is determined at an adaptive testing engine using obtained test data. The adaptation command is sent from the adaptive testing engine to a tool control application. The tool control application uses the adaptation command to control an operation related to the testing of the device.Type: ApplicationFiled: February 26, 2013Publication date: February 27, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David E. Atkinson, Matthew S. Grady, Donald L. LaCroix, David B. Lutton, II, Bradley D. Pepper, Randolph P. Steel
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Publication number: 20140059382Abstract: A method of testing a device is disclosed. Test data is obtained for a device testing program that tests the device. An adaptation command for testing the device is determined at an adaptive testing engine using obtained test data. The adaptation command is sent from the adaptive testing engine to a tool control application. The tool control application uses the adaptation command to control an operation related to the testing of the device.Type: ApplicationFiled: August 22, 2012Publication date: February 27, 2014Applicant: International Business Machines CorporationInventors: David E. Atkinson, Matthew S. Grady, Donald L. LaCroix, David B. Lutton, II, Bradley D. Pepper, Randolph P. Steel
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Publication number: 20130007546Abstract: A method of implementing integrated circuit device testing includes performing baseline testing of a first group of chips using a full set of test patterns, and for chip identified as failing, determining, a score for each test pattern in the full set. The score is indicative of an ability of the test pattern to uniquely identify a failing chip with respect to other test patterns. Following the baseline testing, streamlined testing on a second group of chips is performed, using a reduced set of the test patterns having highest average scores as determined by the baseline testing. Following the streamlined testing, full testing on a third group of chips is performed using the full set of test patterns, and updating the average score for each pattern. Further testing alternates between the streamlined testing and the full testing for additional groups of chips.Type: ApplicationFiled: June 29, 2011Publication date: January 3, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew S. Grady, Mark C. Johnson, Bradley D. Pepper, Dean G. Percy, Joseph C. Pranys
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Patent number: 8087823Abstract: A structure has a heat dissipating feature, an internal temperature measurement device, and a memory. The structure generates heat as power is supplied to the structure, and a threshold voltage of the internal temperature measurement device changes as the temperature of the temperature measurement device changes. The embodiments herein establish a linear relationship between temperature and threshold voltage by heating the structure to a first temperature and recording a first threshold voltage, and then heating the structure to a second temperature and recording a second threshold voltage. From this, the embodiments herein calculate a linear relationship between temperature and threshold voltage. Further, the embodiments herein can calculate the temperatures of the structure based only upon the linear relationship and threshold voltages measured from internal temperature measurement device.Type: GrantFiled: August 18, 2008Date of Patent: January 3, 2012Assignee: International Business Machines CorporationInventors: Francois Aube, Timothy M. Curtin, Matthew S. Grady, Thomas P. Scanlon, Eric N. Smith
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Publication number: 20100042355Abstract: A structure has a heat dissipating feature, an internal temperature measurement device, and a memory. The structure generates heat as power is supplied to the structure, and a threshold voltage of the internal temperature measurement device changes as the temperature of the temperature measurement device changes. The embodiments herein establish a linear relationship between temperature and threshold voltage by heating the structure to a first temperature and recording a first threshold voltage, and then heating the structure to a second temperature and recording a second threshold voltage. From this, the embodiments herein calculate a linear relationship between temperature and threshold voltage. Further, the embodiments herein can calculate the temperatures of the structure based only upon the linear relationship and threshold voltages measured from internal temperature measurement device.Type: ApplicationFiled: August 18, 2008Publication date: February 18, 2010Inventors: Francois Aube, Timothy M. Curtis, Matthew S. Grady, Thomas P. Scanlon, Eric N. Smith
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Patent number: 7620931Abstract: An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of the photomask level design between adjacent integrated circuit element shapes, the designated regions large enough to require placement of fill shapes between the adjacent integrated circuit elements based on fill shape rules, the fill shapes not required for the operation of the integrated circuit; and (c) placing one or more monitor structure shapes of a monitor structure in at least one of the designated regions, the monitor structure not required for the operation of the integrated circuit.Type: GrantFiled: September 24, 2007Date of Patent: November 17, 2009Assignee: International Business Machines CorporationInventors: James W. Adkisson, Greg Bazan, John M. Cohn, Matthew S. Grady, Thomas G. Sopchak, David P. Vallett
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Patent number: 7323278Abstract: An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of the photomask level design between adjacent integrated circuit element shapes, the designated regions large enough to require placement of fill shapes between the adjacent integrated circuit elements based on fill shape rules, the fill shapes not required for the operation of the integrated circuit; and (c) placing one or more monitor structure shapes of a monitor structure in at least one of the designated regions, the monitor structure not required for the operation of the integrated circuit.Type: GrantFiled: March 19, 2007Date of Patent: January 29, 2008Assignee: International Business Machines CorporationInventors: James W. Adkisson, Greg Bazan, John M. Cohn, Matthew S. Grady, Thomas G. Sopchak, David P. Vallett
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Patent number: 7240322Abstract: An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of the photomask level design between adjacent integrated circuit element shapes, the designated regions large enough to require placement of fill shapes between the adjacent integrated circuit elements based on fill shape rules, the fill shapes not required for the operation of the integrated circuit; and (c) placing one or more monitor structure shapes of a monitor structure in at least one of the designated regions, the monitor structure not required for the operation of the integrated circuit.Type: GrantFiled: April 4, 2005Date of Patent: July 3, 2007Assignee: International Business Machines CorporationInventors: James W. Adkisson, Greg Bazan, John M. Cohn, Matthew S. Grady, Thomas G. Sopchak, David P. Vallett
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Patent number: 7194706Abstract: A method is disclosed for designing scan chains in an integrated circuit chip with specific parameter sensitivities to identify fabrication process defects causing test fails and chip yield loss. The composition of scan paths in the integrated circuit chip is biased to allow them to also function as on-product process monitors. The method adds grouping constraints that bias scan chains to have common latch cell usage where possible, and also biases cell routing to constrain scan chain routing to given restricted metal layers for interconnects. The method assembles a list of latch design parameters which are sensitive to process variation or integrity, and formulates a plan for scan chain design which determines the number and the length of scan chains. A model is formulated of scan chain design based upon current state of yield and process integrity, wherein certain latch designs having dominant sensitivities are chosen for specific ones of the scan chains on the chip.Type: GrantFiled: July 27, 2004Date of Patent: March 20, 2007Assignee: International Business Machines CorporationInventors: James W. Adkisson, Greg Bazan, John M. Cohn, Matthew S. Grady, Leendert M. Huisman, Mark D. Jaffe, Phillip J. Nigh, Leah M. P. Pastel, Thomas G. Sopchak, David E. Sweenor, David P. Vallett
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Patent number: 6998866Abstract: A circuit and a method for monitoring defects in an integrated circuit chip. The circuit including a defect monitor portion and a sense element portion, the defect monitor portion either coupled to inputs of sense elements arranged in a chain or coupled between sense elements and forming portions of the chain.Type: GrantFiled: July 27, 2004Date of Patent: February 14, 2006Assignee: International Business Machines CorporationInventors: Greg Bazan, John M. Cohn, Matthew S. Grady, Phillip J. Nigh, Leah M. P. Pastel, Thomas G. Sopchak
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Patent number: 6909274Abstract: A test apparatus and a method for testing an integrated circuit's data storage device's input/output signal pins for alternating current (AC) defects, by providing an interface that will couple each respective individual test contact, in a subset of said contacts, to a select plurality of the data storage input/output signal pins so that when a selected data string is introduced into the integrated circuit so that each input/output pin on a data storage device in the integrated circuit will be tested in sequence whereby the number of contacts required by the tester can be reduced.Type: GrantFiled: April 21, 2003Date of Patent: June 21, 2005Assignee: International Business Machines CorporationInventors: Frank W. Angelotti, Louis B. Bushard, Matthew S. Grady, Scott A. Strissel
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Patent number: 6789032Abstract: A statistical method is described for reliability selection of dies on semiconductor wafers using critical wafer yield parameters. This is combined with other data from the wafer or module level reliability screens (such as voltage screen or burn-in) to obtain the relative latent defect density. Finally the modeled results are compared with actual results to demonstrate confidence in the model.Type: GrantFiled: December 19, 2002Date of Patent: September 7, 2004Assignee: International Business Machines CorporationInventors: Tange N. Barbour, Thomas S. Barnett, Matthew S. Grady, Kathleen G. Purdy
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Publication number: 20040153919Abstract: A test apparatus and a method for testing an integrated circuit's data storage device's input/output signal pins for alternating current (AC) defects, by providing an interface that will couple each respective individual test contact, in a subset of said contacts, to a select plurality of the data storage input/output signal pins so that when a selected data string is introduced into the integrated circuit so that each input/output pin on a data storage device in the integrated circuit will be tested in sequence whereby the number of contacts required by the tester can be reduced.Type: ApplicationFiled: April 21, 2003Publication date: August 5, 2004Inventors: Frank W. Angelotti, Louis B. Bushard, Matthew S. Grady, Scott A. Strissel
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Publication number: 20030151422Abstract: Method for burn-in testing of a wafer having a plurality of dies where the reliability of the fail rate is matched to meet a predetermined criteria. This is accomplished by selecting a subset of dies to be tested and tests are used to weed out the highest number of failures.Type: ApplicationFiled: December 19, 2002Publication date: August 14, 2003Inventors: Thomas S. Barnett, Matthew S. Grady, Kathleen G. Purdy
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Patent number: 6590382Abstract: A test apparatus and a method for testing an integrated circuit's data storage device's input/output signal pins for alternating current (AC) defects, by providing an interface that will couple each respective individual test contact, in a subset of said contacts, to a select plurality of the data storage input/output signal pins so that when a selected data string is introduced into the integrated circuit so that each input/output pin on a data storage device in the integrated circuit will be tested in sequence whereby the number of contacts required by the tester can be reduced.Type: GrantFiled: December 22, 2000Date of Patent: July 8, 2003Assignee: International Business Machines Corp.Inventors: Frank W. Angelotti, Louis B. Bushard, Matthew S. Grady, Scott A. Strissel
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Publication number: 20030120445Abstract: A statistical method is described for reliability selection of dies on semiconductor wafers using critical wafer yield parameters. This is combined with other data from the wafer or module level reliability screens (such as voltage screen or burn-in) to obtain the relative latent defect density. Finally the modeled results are compared with actual results to demonstrate confidence in the model.Type: ApplicationFiled: December 19, 2002Publication date: June 26, 2003Applicant: International Business Machines CorporationInventors: Tange N. Barbour, Thomas S. Barnett, Matthew S. Grady, Kathleen G. Purdy
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Publication number: 20020079880Abstract: A test apparatus and a method for testing an integrated circuit's data storage device's input/output signal pins for alternating current (AC) defects, by providing an interface that will couple each respective individual test contact, in a subset of said contacts, to a select plurality of the data storage input/output signal pins so that when a selected data string is introduced into the integrated circuit so that each input/output pin on a data storage device in the integrated circuit will be tested in sequence whereby the number of contacts required by the tester can be reduced.Type: ApplicationFiled: December 22, 2000Publication date: June 27, 2002Applicant: International Business Machines CorporationInventors: Frank W. Angelotti, Louis B. Bushard, Matthew S. Grady, Scott A. Strissel