Abstract: Processes and systems for use in reverse engineering integrated circuits determine functionality through analysis of junctions responding to external radiation. Semiconductor devices include a number of p-n junctions grouped according to interconnected functional cells. A surface of the semiconductor device is illuminated by radiation, e.g., by a laser or an electron beam, producing electron-hole pairs. Such pairs give rise to detectable currents that can be used to determine locations of irradiated junctions. By scanning a surface of the device in such a manner, a layout of at least some of the junctions can be obtained. The layout can be used to identify functional cells according to a lookup process. By selectively providing input test vectors to the device and repeating the scanning process, first level functional cells can be identified. A netlist of interconnected functional cells can thus be determined and expanded by repeating the process with different test vectors.

Abstract: Processes and systems for use in reverse engineering integrated circuits determine functionality through analysis of junctions responding to external radiation. Semiconductor devices include a number of p-n junctions grouped according to interconnected functional cells. A surface of the semiconductor device is illuminated by radiation, e.g., by a laser or an electron beam, producing electron-hole pairs. Such pairs give rise to detectable currents that can be used to determine locations of irradiated junctions. By scanning a surface of the device in such a manner, a layout of at least some of the junctions can be obtained. The layout can be used to identify functional cells according to a lookup process. By selectively providing input test vectors to the device and repeating the scanning process, first level functional cells can be identified. A netlist of interconnected functional cells can thus be determined and expanded by repeating the process with different test vectors.

Abstract: An insulated gate field effect transistor having a vertically layered elevated source/drain structure includes an electrically conductive suppression region for resistance to hot carrier injection. The device includes a semiconductor substrate of first conductivity type having a gate insulator disposed on the surface of that substrate. A gate electrode, in turn, is disposed on the gate insulator. A lightly doped drain region of second conductivity type is formed in the substrate in alignment with the gate electrode. An electrically conductive suppression region having a first low electrical conductivity is positioned to electrically contact the drain region, but is electrically isolated from the gate electrode and is spaced a first distance from the gate electrode. A heavily doped drain contact also contacts the drain region and is spaced further away from the gate electrode than is the electrically conducted suppression region.