Abstract: Emulating scratchpad functionality using caches in processor-based devices is disclosed. In one aspect, each cache line within a cache of a processor-based device is associated with a corresponding scratchpad indicator indicating whether the corresponding cache line is exempt from the replacement policy used to select a cache line for eviction. Upon receiving data that corresponds to a memory access operation indicated as requiring scratchpad functionality, the cache controller stores the data in a cache line of the cache, and then sets the corresponding scratchpad indicator for the cache line. Subsequently, the cache controller emulates scratchpad functionality by allowing conventional memory read and write operations to be performed on the cache line, but does not apply its replacement policy to that cache line when selecting a cache line as a candidate for eviction. In this manner, the cache line may remain in the cache for use as scratchpad memory by software.

Abstract: In-line memory module (IMM) computing nodes with an embedded processor(s) to support local processing of memory-based operations for lower latency and reduced power consumption, and related methods are disclosed. The IMM computing node that includes one or more memory chips mounted on a circuit board. The IMM computing node also includes one or more embedded processor(s) on the circuit board that are each interfaced to at least one memory chip among the one or more memory chips. The processor(s) can be configured to access its interfaced memory chip(s) through an internal memory bus on the circuit board to perform processing onboard the IMM computing node in an offload computing access mode. The embedded processors(s) can also be configured to forward memory access requests received from an external processor to the memory chip(s) for data storage and retrieval in a transparent access mode without further local processing of the memory access requests.

Abstract: Emulating scratchpad functionality using caches in processor-based devices is disclosed. In one aspect, each cache line within a cache of a processor-based device is associated with a corresponding scratchpad indicator indicating whether the corresponding cache line is exempt from the replacement policy used to select a cache line for eviction. Upon receiving data that corresponds to a memory access operation indicated as requiring scratchpad functionality, the cache controller stores the data in a cache line of the cache, and then sets the corresponding scratchpad indicator for the cache line. Subsequently, the cache controller emulates scratchpad functionality by allowing conventional memory read and write operations to be performed on the cache line, but does not apply its replacement policy to that cache line when selecting a cache line as a candidate for eviction. In this manner, the cache line may remain in the cache for use as scratchpad memory by software.

Abstract: In-line memory module (IMM) computing nodes with an embedded processor(s) to support local processing of memory-based operations for lower latency and reduced power consumption, and related methods are disclosed. The IMM computing node that includes one or more memory chips mounted on a circuit board. The IMM computing node also includes one or more embedded processor(s) on the circuit board that are each interfaced to at least one memory chip among the one or more memory chips. The processor(s) can be configured to access its interfaced memory chip(s) through an internal memory bus on the circuit board to perform processing onboard the IMM computing node in an offload computing access mode. The embedded processors(s) can also be configured to forward memory access requests received from an external processor to the memory chip(s) for data storage and retrieval in a transparent access mode without further local processing of the memory access requests.

Abstract: A memory system supporting programmable selective access to subsets of parallel-arranged memory chips for efficient memory accesses is disclosed. A memory controller is programmable to selectively control a number of parallel-arranged memory chips in the memory system activated in a grouping for a memory access based on a memory access policy. The memory access policy is based on the number of memory chips to be activated to achieve the desired data line size for a given memory access. This programmability of the memory controller is made possible by separate dedicated chip select lines being coupled to each memory chip. Being able to only activate a subset of the memory chips for a memory access allows conservation of data bus bandwidth and power that would otherwise by consumed by asserting unused data on the data buses.