Abstract: Impedance control, and the uniformity of electrical and mechanical characteristics in electronic packaging are becoming more important as chip and bus speeds increase and manufacturing processes evolve. Current state of the art design and manufacture processes inherently introduce physical dielectric thickness variations into PCB cross sections. These thickness variations between the ground reference plane(s) and the signal layer(s) inject undesirable characteristic impedance variations and undesirable mechanical variations in thickness and surface topology. Therefore a multilayer electronic structure and a method of manufacture is presented.

Abstract: Impedance control, and the uniformity of electrical and mechanical characteristics in electronic packaging are becoming more important as chip and bus speeds increase and manufacturing processes evolve. Current state of the art design and manufacture processes inherently introduce physical dielectric thickness variations into multilayer cross sections. These thickness variations between the ground reference plane(s) and the signal layer(s) inject undesirable characteristic impedance variations and undesirable mechanical variations in thickness and surface topology. Therefore a multilayer structure and a method of manufacture are presented.

Abstract: A method and connector housing are provided for implementing an impedance gradient connector for board-to-board applications. The impedance gradient connector housing includes a plurality of impedance zones with a first impedance zone including a first mating face with a first Printed Circuit Board (PCB) and with a second impedance zone including a second mating face with a second PCB. Each of the respective predefined impedance zones including the first mating face and the second mating face include a selected impedance to minimize impedance mismatch with associated PCBs.

Abstract: A method and connector housing are provided for implementing an impedance gradient connector for board-to-board applications. The impedance gradient connector housing includes a plurality of impedance zones with a first impedance zone including a first mating face with a first Printed Circuit Board (PCB) and with a second impedance zone including a second mating face with a second PCB. Each of the respective predefined impedance zones including the first mating face and the second mating face include a selected impedance to minimize impedance mismatch with associated PCBs.

Abstract: A method and mesh reference applications are provided for implementing Z-axis cross-talk reduction. A mesh reference plane including a grid of mesh traces is formed with the mesh traces having selected thickness and width dimensions effective for reference current-flow distribution. An electrically conductive coating is deposited to fill the mesh electrical holes in the mesh reference plane to reduce cross-talk, substantially without affecting mechanical flexibility.

Abstract: A flexible printed circuit assembly with a fluorocarbon dielectric layer and an adhesive layer with reduced thickness. The flexible printed circuit assembly includes a first dielectric layer and a signal trace disposed on the first dielectric layer. An adhesive layer with a thickness smaller than a height of the signal trace is disposed on the first dielectric layer, so that only a portion of a side surface of the signal trace is covered. A second dielectric layer made of fluorocarbon is disposed on the adhesive layer, covering a remaining portion of the side surface of the signal trace and a top surface of the signal trace.

Abstract: Impedance control, and the uniformity of electrical and mechanical characteristics in electronic packaging are becoming more important as chip and bus speeds increase and manufacturing processes evolve. Current state of the art design and manufacture processes inherently introduce physical dielectric thickness variations into PCB cross sections. These thickness variations between the ground reference plane(s) and the signal layer(s) inject undesirable characteristic impedance variations and undesirable mechanical variations in thickness and surface topology. Therefore a process of generating equalization data and a design structure for multilayer electronic structures is presented.

Abstract: Impedance control, and the uniformity of electrical and mechanical characteristics in electronic packaging are becoming more important as chip and bus speeds increase and manufacturing processes evolve. Current state of the art design and manufacture processes inherently introduce physical dielectric thickness variations into PCB cross sections. These thickness variations between the ground reference plane(s) and the signal layer(s) inject undesirable characteristic impedance variations and undesirable mechanical variations in thickness and surface topology. Therefore a multilayer electronic structure and a method of manufacture is presented.

Abstract: Impedance control, and the uniformity of electrical and mechanical characteristics in electronic packaging are becoming more important as chip and bus speeds increase and manufacturing processes evolve. Current state of the art design and manufacture processes inherently introduce physical dielectric thickness variations into PCB cross sections. These thickness variations between the ground reference plane(s) and the signal layer(s) inject undesirable characteristic impedance variations and undesirable mechanical variations in thickness and surface topology. Therefore a process of generating equalization data and a design structure for multilayer electronic structures is presented.

Abstract: Impedance control, and the uniformity of electrical and mechanical characteristics in electronic packaging are becoming more important as chip and bus speeds increase and manufacturing processes evolve. Current state of the art design and manufacture processes inherently introduce physical dielectric thickness variations into multilayer cross sections. These thickness variations between the ground reference plane(s) and the signal layer(s) inject undesirable characteristic impedance variations and undesirable mechanical variations in thickness and surface topology. Therefore a multilayer structure and a method of manufacture are presented.

Abstract: A flexible printed circuit assembly with a fluorocarbon dielectric layer and an adhesive layer with reduced thickness. The flexible printed circuit assembly includes a first dielectric layer and a signal trace disposed on the first dielectric layer. An adhesive layer with a thickness smaller than a height of the signal trace is disposed on the first dielectric layer, so that only a portion of a side surface of the signal trace is covered. A second dielectric layer made of fluorocarbon is disposed on the adhesive layer, covering a remaining portion of the side surface of the signal trace and a top surface of the signal trace.

Abstract: A method and apparatus implement reduced noise coupling effects on single ended clocks, and a design structure on which the subject circuit resides is provided. A clock receiver includes a clock voltage reference that is generated from received clock peaks and valleys of a received input clock signal. The received clock peaks (VT) and the received clock valleys (VB) are continuously sampled. The clock voltage reference is set, for example, equal to an average of VT and VB; or ((VT+VB)/2).

Abstract: A method and structures with an EMI shielding electrically conductive coating are provided for implementing EMI shielding for rigid cards and flexible circuits. An EMI shielding electrically conductive coating is deposited on an outer layer, for example, using a vacuum sputtering deposition, chemical vapor deposition (CVD) or physical vapor deposition (PVD) process. A solder mask is applied. Mechanically cleaning removes the sputtered copper coating in areas of the outer layer that are not protected by the solder mask.

Abstract: A method and structure are provided for implementing flexible circuits of various electronic packages and circuit applications. A meshed reference plane includes a variable mesh pitch arranged for control of mechanical flexibility. A dielectric core separates a signal layer from the variable pitch meshed reference plane. An electrically conductive coating covers the surface of the variable pitch meshed reference plane yielding substantially constant signal impedance for the signal layer.

Abstract: A method and apparatus are provided for implementing automatic-calibration of a Time Domain Reflectometer (TDR) probing apparatus. A calibration procedure is performed automatically each time a TDR probe is moved from a device under test (DUT). A current calibration TDR waveform is obtained and compared with a reference calibration TDR waveform, checking for deviations between the current and reference measurements. If a deviation is detected, then the user is notified and calibration is failed.

Abstract: A method and structures with an EMI shielding electrically conductive coating are provided for implementing EMI shielding for rigid cards and flexible circuits. An EMI shielding electrically conductive coating is deposited on an outer layer, for example, using a vacuum sputtering deposition, chemical vapor deposition (CVD) or physical vapor deposition (PVD) process. A solder mask is applied. Mechanically cleaning removes the sputtered copper coating in areas of the outer layer that are not protected by the solder mask.

Abstract: A method and apparatus are provided for implementing characteristic impedance discontinuity reduction in customized high-speed flexible circuit applications. A curved artwork region is selected and selected cells are scanned. An area on opposite sides of a signal wire within each cell is determined. The identified areas are compared using a user defined delta value. If the compared areas differ greater than the user defined delta value, then a coordinate change is computed for moving the signal wire to reduce characteristic impedance discontinuity.

Abstract: A method and apparatus are provided for implementing automatic-calibration of a Time Domain Reflectometer (TDR) probing apparatus. A calibration procedure is performed automatically each time a TDR probe is moved from a device under test (DUT). A current calibration TDR waveform is obtained and compared with a reference calibration TDR waveform, checking for deviations between the current and reference measurements. If a deviation is detected, then the user is notified and calibration is failed.

Abstract: A method, apparatus and computer program product are provided for implementing high frequency return current paths utilizing decoupling capacitors within electronic packages. Electronic package physical design data are received for identifying a board layout. For each of a plurality of cells in a grid of a set cell size within the identified board layout, a respective number of signal vias are identified. A ratio of signal vias to return current paths is calculated for each of the plurality of cells. Each cell having a calculated ratio greater than a target ratio is identified. One or more decoupling capacitors are selectively added within each of the identified cells to provide high frequency return current paths.

Abstract: A modular heat sink decoupling capacitor array includes a plurality of modules, each defining parallel distributed decoupling plates, and each module forming a heat sink fi. Each module includes multiple spaced apart contacts for providing low inductance connections with an associated device. A power distribution interposer module is attached to a heat sink surface of the modular decoupling capacitor. The interposer module is used for implementing power delivery without using valuable ball grid array (BGA) connections and printed circuit board (PCB) layers.