Abstract: The disclosed voltage regulator includes multiple voltage converter circuits. Each of the voltage converter circuits can be configured to operate at respective switching frequencies to deliver current to an output supply voltage. The voltage regulator can include a control circuit that regulates the output supply voltage using the voltage converter circuits. Various other methods and systems are also disclosed.

Abstract: A power converter assembly includes a stack of circuit components to convert an input voltage into an output voltage. The stack of circuit components may include: a first component layer including driver circuitry; a second component layer including multiple switches controlled by the driver circuitry in the first component layer; and a third component layer disposed between the first component layer and the second component layer, the third component layer comprising at least one capacitor component to support conversion of the input voltage into the output voltage. In another implementation, the power converter assembly includes: a first component layer including at least one capacitor component of the power converter; a second component layer coupled to the first component layer, the second component layer including driver circuitry and multiple switches; and a third component layer including at least one inductor.

Abstract: Chip packages are described herein that includes chiplets embedded in a core of a substrate of the chip package, such as a package substrate or an interposer. In one example, the chiplet includes voltage regulation circuitry that is coupled through a substrate core embedded inductor to an integrated circuit (IC) die mounted to the substrate.

Abstract: A controller for a SIMO DC-DC converter operable in CCM and DCM receives a signal representative of an inductor current, and signals representative of a first and a second DC-DC converter output. The controller has a first and second output adapted to control electronic switches coupled to a first and second output filter, and a third and fourth output adapted to control current in an inductor. The controller controls the outputs based upon the inputs by determining a desired PWL inductor current and current waveform, and determines pulsewidths of the outputs, to match the inductor current to the desired PWL. A timer controls pulsewidths of the outputs and the controller dynamically selects DCM or CCM to maintain the first and second DC-DC converter outputs at predetermined levels. In embodiments, the desired PWL inductor current is one or both of a desired valley current and a desired peak current.

Abstract: A controller for a SIMO DC-DC converter operable in CCM and DCM receives a signal representative of an inductor current, and signals representative of a first and a second DC-DC converter output. The controller has a first and second output adapted to control electronic switches coupled to a first and second output filter, and a third and fourth output adapted to control current in an inductor. The controller controls the outputs based upon the inputs by determining a desired PWL inductor current and current waveform, and determines pulsewidths of the outputs, to match the inductor current to the desired PWL. A timer controls pulsewidths of the outputs and the controller dynamically selects DCM or CCM to maintain the first and second DC-DC converter outputs at predetermined levels. In embodiments, the desired PWL inductor current is one or both of a desired valley current and a desired peak current.

Abstract: Various embodiments of the invention provide for cancellation of a residue amplifier output charging current at the reference voltage source of the reference buffer thereby preventing the charging current from altering the effective reference voltage of a reference buffer. In certain embodiments, current cancellation is accomplished by subtracting a current of the same magnitude.

Abstract: Various embodiments of the invention provide for cancellation of a residue amplifier output charging current at the reference voltage source of the reference buffer thereby preventing the charging current from altering the effective reference voltage of a reference buffer. In certain embodiments, current cancellation is accomplished by subtracting a current of the same magnitude.

Abstract: Various embodiments of the invention provide for cancellation of a residue amplifier output charging current at the reference voltage source of the reference buffer thereby preventing the charging current from altering the effective reference voltage of a reference buffer. In certain embodiments, current cancellation is accomplished by subtracting a current of the same magnitude.

Abstract: Described is a compact, lower power gated ring oscillator time-to-digital converter that achieves first order noise shaping of quantization noise using a digital implementation. The gated ring oscillator time-to-digital converter includes a plurality of delay stages configured to enable propagation of a transitioning signal through the delay stages during an enabled state and configured to inhibit propagation of the transitioning signal through the delay stages during a disabled state. Delay stages are interconnected to allow sustained transitions to propagate through the delay stages during the enabled state and to preserve a state of the gated ring oscillator time-to-digital converter during the disabled state. The state represents a time resolution that is finer than the delay of at least one of the delay stages. A measurement module determines the number of transitions of the delay stages.

Abstract: Described is a compact, lower power gated ring oscillator time-to-digital converter that achieves first order noise shaping of quantization noise using a digital implementation. The gated ring oscillator time-to-digital converter includes a plurality of delay stages configured to enable propagation of a transitioning signal through the delay stages during an enabled state and configured to inhibit propagation of the transitioning signal through the delay stages during a disabled state. Delay stages are interconnected to allow sustained transitions to propagate through the delay stages during the enabled state and to preserve a state of the gated ring oscillator time-to-digital converter during the disabled state. The state represents a time resolution that is finer than the delay of at least one of the delay stages. A measurement module determines the number of transitions of the delay stages.