Patents by Inventor Matthew T. Currie

Matthew T. Currie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Strained channel dynamic random access memory devices
    Patent number: 8253181
    Abstract: DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.
    Type: Grant
    Filed: July 3, 2008
    Date of Patent: August 28, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mayank Bulsara, Matthew T. Currie, Anthony J. Lochtefeld
  • RF circuits including transistors having strained material layers
    Patent number: 8247798
    Abstract: Circuits for processing radio frequency (“RF”) and microwave signals are fabricated using field effect transistors (“FETs”) that have one or more strained channel layers disposed on one or more planarized substrate layers. FETs having such a configuration exhibit improved values for, for example, transconductance and noise figure. RF circuits such as, for example, voltage controlled oscillators (“VCOs”), low noise amplifiers (“LNAs”), and phase locked loops (“PLLs”) built using these FETs also exhibit enhanced performance.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: August 21, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Glyn Braithwaite, Richard Hammond, Matthew T. Currie
  • Method of producing high quality relaxed silicon germanium layers
    Patent number: 8187379
    Abstract: A method for minimizing particle generation during deposition of a graded Si1-xGex layer on a semiconductor material includes providing a substrate in an atmosphere including a Si precursor and a Ge precursor, wherein the Ge precursor has a decomposition temperature greater than germane, and depositing the graded Si1-xGex layer having a final Ge content of greater than about 0.15 and a particle density of less than about 0.3 particles/cm2 on the substrate.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: May 29, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eugene Fitzgerald, Richard Westhoff, Matthew T. Currie, Christopher J. Vineis, Thomas A. Langdo
  • Hybrid fin field-effect transistor structures and related methods
    Patent number: 8183627
    Abstract: Semiconductor-on-insulator structures facilitate the fabrication of devices, including MOSFETs that are at least partially depleted during operation and FinFETs including bilayer fins and/or crystalline oxide.
    Type: Grant
    Filed: May 22, 2008
    Date of Patent: May 22, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Matthew T. Currie
  • Reacted Conductive Gate Electrodes and Methods of Making the Same
    Publication number: 20120098054
    Abstract: A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal to the semiconductor layer and a portion distal to the semiconductor layer. The distal portion includes the first material and the second material. A metal layer formed adjacent to the relaxed semiconductor layer and adjacent to the distal portion of the contact is simultaneously reacted with the relaxed semiconductor layer and with the distal portion of the contact to provide metallic contact material.
    Type: Application
    Filed: January 3, 2012
    Publication date: April 26, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Matthew T. Currie, Richard Hammond
  • Semiconductor heterostructures having reduced dislocation pile-ups and related methods
    Patent number: 8129747
    Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: March 6, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Richard Westhoff, Vicky Yang, Matthew T. Currie, Christopher J. Vineis, Christopher Leitz
  • Reacted conductive gate electrodes
    Patent number: 8129821
    Abstract: A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal to the semiconductor layer and a portion distal to the semiconductor layer. The distal portion includes the first material and the second material. A metal layer formed adjacent to the relaxed semiconductor layer and adjacent to the distal portion of the contact is simultaneously reacted with the relaxed semiconductor layer and with the distal portion of the contact to provide metallic contact material.
    Type: Grant
    Filed: September 17, 2004
    Date of Patent: March 6, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Matthew T. Currie, Richard Hammond
  • Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
    Patent number: 8106380
    Abstract: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: January 31, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Matthew T. Currie, Anthony J. Lochtefeld, Richard Hammond, Eugene Fitzgerald
  • METHODS FOR FORMING SEMICONDUCTOR DEVICE STRUCTURES
    Publication number: 20110318893
    Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
    Type: Application
    Filed: September 7, 2011
    Publication date: December 29, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Anthony J. Lochtefeld, Thomas A. Langdo, Richard Hammond, Matthew T. Currie, Eugene A. Fitzgerald
  • III-V semiconductor device structures
    Patent number: 8026534
    Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: September 27, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Thomas A. Langdo, Matthew T. Currie, Richard Hammond, Anthony J. Lochtefeld, Eugene A. Fitzgerald
  • Method of Producing High Quality Relaxed Silicon Germanium Layers
    Publication number: 20110177681
    Abstract: A method for minimizing particle generation during deposition of a graded Si1-xGex layer on a semiconductor material includes providing a substrate in an atmosphere including a Si precursor and a Ge precursor, wherein the Ge precursor has a decomposition temperature greater than germane, and depositing the graded Si1-xGex layer having a final Ge content of greater than about 0.15 and a particle density of less than about 0.3 particles/cm2 on the substrate.
    Type: Application
    Filed: March 29, 2011
    Publication date: July 21, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eugene A. Fitzgerald, Richard Westhoff, Matthew T. Currie, Christopher J. Vineis, Thomas A. Langdo
  • Method of producing high quality relaxed silicon germanium layers
    Patent number: 7955435
    Abstract: A method for minimizing particle generation during deposition of a graded Si.sub.1-xGe.sub.x layer on a semiconductor material includes providing a substrate in an atmosphere including a Si precursor and a Ge precursor, wherein the Ge precursor has a decomposition temperature greater than germane, and depositing the graded Si.sub.1-xGe.sub.x layer having a final Ge content of greater than about 0.15 and a particle density of less than about 0.3 particles/cm.sup.2 on the substrate.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: June 7, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eugene Fitzgerald, Richard Westhoff, Matthew T. Currie, Christopher J. Vineis, Thomas A. Langdo
  • III-V Semiconductor Device Structures
    Publication number: 20110073908
    Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
    Type: Application
    Filed: October 19, 2010
    Publication date: March 31, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Anthony J. Lochtefeld, Thomas A. Langdo, Richard Hammond, Matthew T. Currie, Eugene A. Fitzgerald
  • Lattice-Mismatched Semiconductor Structures with Reduced Dislocation Defect Densities and Related Methods for Device Fabrication
    Publication number: 20110049568
    Abstract: Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.
    Type: Application
    Filed: July 28, 2010
    Publication date: March 3, 2011
    Inventors: Anthony J. Lochtefeld, Matthew T. Currie, Zhiyuan Cheng, James Fiorenza, Glyn Braithwaite, Thomas A. Langdo
  • Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
    Patent number: 7846802
    Abstract: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: December 7, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Matthew T. Currie, Anthony J. Lochtefeld, Richard Hammond, Eugene A. Fitzgerald
  • Methods for forming III-V semiconductor device structures
    Patent number: 7838392
    Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: November 23, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Thomas A. Langdo, Matthew T. Currie, Richard Hammond, Anthony J. Lochtefeld, Eugene A. Fitzgerald
  • Semiconductor heterostructures having reduced dislocation pile-ups and related methods
    Patent number: 7829442
    Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: November 9, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Richard Westhoff, Vicky K. Yang, Matthew T. Currie, Christopher Vineis, Christopher Leitz
  • Method of Producing High Quality Relaxed Silicon Germanium Layers
    Publication number: 20100206216
    Abstract: A method for minimizing particle generation during deposition of a graded Si.sub.1-xGe.sub.x layer on a semiconductor material includes providing a substrate in an atmosphere including a Si precursor and a Ge precursor, wherein the Ge precursor has a decomposition temperature greater than germane, and depositing the graded Si.sub.1-xGe.sub.x layer having a final Ge content of greater than about 0.15 and a particle density of less than about 0.3 particles/cm.sup.2 on the substrate.
    Type: Application
    Filed: February 24, 2010
    Publication date: August 19, 2010
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eugene A. Fitzgerald, Richard Westhoff, Matthew T. Currie, Christopher J. Vineis, Thomas A. Langdo
  • Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
    Patent number: 7776697
    Abstract: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: August 17, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Matthew T. Currie, Anthony J. Lochtefeld, Richard Hammond, Eugene A. Fitzgerald
  • Method of producing high quality relaxed silicon germanium layers
    Patent number: 7674335
    Abstract: A method for minimizing particle generation during deposition of a graded Si1?xGex layer on a semiconductor material includes providing a substrate in an atmosphere including a Si precursor and a Ge precursor, wherein the Ge precursor has a decomposition temperature greater than germane, and depositing the graded Si1?xGex layer having a final Ge content of greater than about 0.15 and a particle density of less than about 0.3 particles/cm2 on the substrate.
    Type: Grant
    Filed: March 9, 2006
    Date of Patent: March 9, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eugene A. Fitzgerald, Richard Westhoff, Matthew T. Currie, Christopher J. Vineis, Thomas A. Langdo