Patents by Inventor Matthew T. Herrick

Matthew T. Herrick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8173505
    Abstract: A method includes forming a first layer of gate material over a semiconductor substrate; forming a hard mask layer over the first layer; forming an opening; forming a charge storage layer over the hard mask layer and within the opening; forming a second layer of gate material over the charge storage layer; removing a portion of the second layer and a portion of the charge storage layer which overlie the hard mask layer, wherein a second portion of the second layer remains within the opening; forming a patterned masking layer over the hard mask layer and over the second portion, wherein the patterned masking layer defines both a first and second bitcell; and forming the first and second bitcell using the patterned masking layer, wherein each of the first and second bitcell comprises a select gate made from the first layer and a control gate made from the second layer.
    Type: Grant
    Filed: October 20, 2008
    Date of Patent: May 8, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Matthew T. Herrick, Ko-Min Chang, Gowrishankar L. Chindalore, Sung-Taeg Kang
  • Patent number: 7838363
    Abstract: A method forms a split gate memory cell by providing a semiconductor substrate and forming an overlying select gate. The select gate has a predetermined height and is electrically insulated from the semiconductor substrate. A charge storing layer is subsequently formed overlying and adjacent to the select gate. A control gate is subsequently formed adjacent to and separated from the select gate by the charge storing layer. The charge storing layer is also positioned between the control gate and the semiconductor substrate. The control gate initially has a height greater than the predetermined height of the select gate. The control gate is recessed to a control gate height that is less than the predetermined height of the select gate. A source and a drain are formed in the semiconductor substrate.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: November 23, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Robert F. Steimle, Gowrishankar L. Chindalore, Matthew T. Herrick
  • Patent number: 7745298
    Abstract: A method for forming a via includes forming a gate electrode over a semiconductor substrate, forming a source/drain region in the semiconductor substrate adjacent the gate electrode, forming a silicide region in the source/drain region, forming a post-silicide spacer adjacent the gate electrode after forming the silicide region, forming an interlayer dielectric layer over the gate electrode, the post-silicide spacer, and the silicide region, and forming a conductive via in the interlayer dielectric layer, extending to the silicide region.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: June 29, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Tab A. Stephens, Olubunmi O. Adetutu, Paul A. Grudowski, Matthew T. Herrick
  • Publication number: 20100099246
    Abstract: A method includes forming a first layer of gate material over a semiconductor substrate; forming a hard mask layer over the first layer; forming an opening; forming a charge storage layer over the hard mask layer and within the opening; forming a second layer of gate material over the charge storage layer; removing a portion of the second layer and a portion of the charge storage layer which overlie the hard mask layer, wherein a second portion of the second layer remains within the opening; forming a patterned masking layer over the hard mask layer and over the second portion, wherein the patterned masking layer defines both a first and second bitcell; and forming the first and second bitcell using the patterned masking layer, wherein each of the first and second bitcell comprises a select gate made from the first layer and a control gate made from the second layer.
    Type: Application
    Filed: October 20, 2008
    Publication date: April 22, 2010
    Inventors: Matthew T. herrick, Ko-Min Chang, Gowrishankar L. Chindalore, Sung-Taeg Kang
  • Publication number: 20090142895
    Abstract: A method for forming a via includes forming a gate electrode over a semiconductor substrate, forming a source/drain region in the semiconductor substrate adjacent the gate electrode, forming a silicide region in the source/drain region, forming a post-silicide spacer adjacent the gate electrode after forming the silicide region, forming an interlayer dielectric layer over the gate electrode, the post-silicide spacer, and the silicide region, and forming a conductive via in the interlayer dielectric layer, extending to the silicide region.
    Type: Application
    Filed: November 30, 2007
    Publication date: June 4, 2009
    Inventors: Tab A. Stephens, Olubunmi O. Adetutu, Paul A. Grudowski, Matthew T. Herrick
  • Publication number: 20090111229
    Abstract: A method forms a split gate memory cell by providing a semiconductor substrate and forming an overlying select gate. The select gate has a predetermined height and is electrically insulated from the semiconductor substrate. A charge storing layer is subsequently formed overlying and adjacent to the select gate. A control gate is subsequently formed adjacent to and separated from the select gate by the charge storing layer. The charge storing layer is also positioned between the control gate and the semiconductor substrate. The control gate initially has a height greater than the predetermined height of the select gate. The control gate is recessed to a control gate height that is less than the predetermined height of the select gate. A source and a drain are formed in the semiconductor substrate.
    Type: Application
    Filed: October 31, 2007
    Publication date: April 30, 2009
    Inventors: Robert F. Steimle, Gowrishankar L. Chindalore, Matthew T. Herrick
  • Patent number: 7416945
    Abstract: A method forms a split gate memory device. A layer of select gate material over a substrate is patterned to form a first sidewall. A sacrificial spacer is formed adjacent to the first sidewall. Nanoclusters are formed over the substrate including on the sacrificial spacer. The sacrificial spacer is removed after the forming the layer of nanoclusters, wherein nanoclusters formed on the sacrificial spacer are removed and other nanoclusters remain. A layer of control gate material is formed over the substrate after the sacrificial spacer is removed. A control gate of a split gate memory device is formed from the layer of control gate material, wherein the control gate is located over remaining nanoclusters.
    Type: Grant
    Filed: February 19, 2007
    Date of Patent: August 26, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ramachandran Muralidhar, Rajesh A. Rao, Matthew T. Herrick, Narayanan C. Ramani, Robert F. Steimle
  • Publication number: 20080199996
    Abstract: A method forms a split gate memory device. A layer of select gate material over a substrate is patterned to form a first sidewall. A sacrificial spacer is formed adjacent to the first sidewall. Nanoclusters are formed over the substrate including on the sacrificial spacer. The sacrificial spacer is removed after the forming the layer of nanoclusters, wherein nanoclusters formed on the sacrificial spacer are removed and other nanoclusters remain. A layer of control gate material is formed over the substrate after the sacrificial spacer is removed. A control gate of a split gate memory device is formed from the layer of control gate material, wherein the control gate is located over remaining nanoclusters.
    Type: Application
    Filed: February 19, 2007
    Publication date: August 21, 2008
    Inventors: Ramachandran Muralidhar, Rajesh A. Rao, Matthew T. Herrick, Narayanan C. Ramani, Robert F. Steimle
  • Patent number: 7323094
    Abstract: An electroplating system (30) and process makes electrical current density across a semiconductor device substrate (20) surface more uniform during plating to allow for a more uniform or tailored deposition of a conductive material. The electrical current density modifiers (364 and 37) reduce the electrical current density near the edge of the substrate (20). By reducing the current density near the edge of the substrate (20), the plating becomes more uniform or can be tailored so that slightly more material is plated near the center of the substrate (20). The system can also be modified so that the material that plates on electrical current density modifier portions (364) of structures (36) can be removed without having to disassemble any portion of the head (35) or otherwise remove the structures (36) from the system. This in-situ cleaning reduces the amount of equipment downtime, increases equipment lifetime, and reduces particle counts.
    Type: Grant
    Filed: August 14, 2002
    Date of Patent: January 29, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Cindy Reidsema Simpson, Matthew T. Herrick, Gregory S. Etherington, James Derek Legg
  • Patent number: 6500324
    Abstract: An electroplating system (30) and process makes electrical current density across, a semiconductor device substrate (20) surface more uniform during plating to allow for a more uniform or tailored deposition of a conductive material. The electrical current density modifiers (364 and 37) reduce the electrical current density near the edge of the substrate (20). By reducing the current density near the edge of the substrate (20), the plating becomes more uniform or can be tailored so that slightly more material is plated near the center of the substrate (20). The system can also be modified so that the material that electrical current density modifier portions (364) on structures (36) can be removed without having to disassemble any portion of the head (35) or otherwise remove the structures (36) from the system. This in-situ cleaning reduces the amount of equipment downtime, increases equipment lifetime, and reduces particle counts.
    Type: Grant
    Filed: May 1, 2000
    Date of Patent: December 31, 2002
    Assignee: Motorola, Inc.
    Inventors: Cindy Reidsema Simpson, Matthew T. Herrick, Gregory S. Etherington, James Derek Legg
  • Publication number: 20020195347
    Abstract: An electroplating system (30) and process makes electrical current density across a semiconductor device substrate (20) surface more uniform during plating to allow for a more uniform or tailored deposition of a conductive material. The electrical current density modifiers (364 and 37) reduce the electrical current density near the edge of the substrate (20). By reducing the current density near the edge of the substrate (20), the plating becomes more uniform or can be tailored so that slightly more material is plated near the center of the substrate (20). The system can also be modified so that the material that electrical current density modifier portions (364) on structures (36) can be removed without having to disassemble any portion of the head (35) or otherwise remove the structures (36) from the system. This in-situ cleaning reduces the amount of equipment downtime, increases equipment lifetime, and reduces particle counts.
    Type: Application
    Filed: August 14, 2002
    Publication date: December 26, 2002
    Inventors: Cindy Reidsema Simpson, Matthew T. Herrick, Gregory S. Etherington, James Derek Legg
  • Patent number: 6297155
    Abstract: A method for electroplating a copper layer (118) over a wafer (20) powers a cathode of an electroplating system (10) in a manner that obtains improved copper interconnects. A control system (34) powers the cathode of the system (10) with a mix of two or more of: (i) positive low-powered DC cycles (201 or 254); (ii) positive high-powered DC cycles (256 or 310); (iii) low-powered, pulsed, positive-power cycles (306 or 530); (iv) high-powered, pulsed, positive-powered cycles (212, 252, 302, or 352); and/or (v) negative pulsed cycles (214, 304, 510, 528, or 532). The collection of these cycles functions to electroplate copper or a like metal (118) onto the wafer (20). During electroplating, insitu process control and/or endpointing (506, 512, or 520) is performed to further improve the resulting copper interconnect.
    Type: Grant
    Filed: May 3, 1999
    Date of Patent: October 2, 2001
    Assignee: Motorola Inc.
    Inventors: Cindy Reidsema Simpson, Robert Douglas Mikkola, Matthew T. Herrick, Brett Caroline Baker, David Moralez Pena, Edward Acosta, Rina Chowdhury, Marijean Azrak, Cindy Kay Goldberg, Mohammed Rabiul Islam
  • Patent number: 6174425
    Abstract: An electroplating system (30) and process makes electrical current density across a semiconductor device substrate (20) surface more uniform during plating to allow for a more uniform or tailored deposition of a conductive material. The electrical current density modifiers (364 and 37) reduce the electrical current density near the edge of the substrate (20). By reducing the current density near the edge of the substrate (20), the plating becomes more uniform or can be tailored so that slightly more material is plated near the center of the substrate (20). The system can also be modified so that the material that electrical current density modifier portions (364) on structures (36) can be removed without having to disassemble any portion of the head (35) or otherwise remove the structures (36) from the system. This in-situ cleaning reduces the amount of equipment downtime, increases equipment lifetime, and reduces particle counts.
    Type: Grant
    Filed: May 14, 1997
    Date of Patent: January 16, 2001
    Assignee: Motorola, Inc.
    Inventors: Cindy Reidsema Simpson, Matthew T. Herrick, Gregory S. Etherington, James Derek Legg