Patents by Inventor Matthew T. Shoudy
Matthew T. Shoudy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11688632Abstract: Semiconductor devices and methods for forming semiconductor devices include opening at least one contact via through a sacrificial material down to contacts. Sides of the at least one contact via are lined by selectively depositing a barrier on the sacrificial material, the barrier extending along sidewalls of the at least one contact via from a top surface of the sacrificial material down to a bottom surface of the sacrificial material proximal to the contacts such that the contacts remain exposed. A conductive material is deposited in the at least one contact via down to the contacts to form stacked contacts having the hard mask on sides thereof. The sacrificial material is removed.Type: GrantFiled: December 29, 2020Date of Patent: June 27, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alex Joseph Varghese, Marc A. Bergendahl, Andrew M. Greene, Dallas Lea, Matthew T. Shoudy, Yann Mignot, Ekmini A. De Silva, Gangadhara Raja Muthinti
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Publication number: 20230200265Abstract: A phase change memory structure including a bottom electrode; a top electrode; a first phase change material between the bottom electrode and the top electrode; a first dielectric surrounding the first phase change material; a second dielectric surrounding the top electrode, the second dielectric having selective adhesion to a metal as compared to the first phase change material; a first metal feature contacting the bottom electrode; and a second metal feature contacting the top electrode.Type: ApplicationFiled: December 16, 2021Publication date: June 22, 2023Inventors: Kevin W. Brew, Injo Ok, Sanjay C. Mehta, Matthew T. Shoudy, Nicole Saulnier, Iqbal Rashid Saraf
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Publication number: 20230171114Abstract: A physical unclonable function (PUF) device includes a ring oscillator, a plurality of band-pass filters, a demultiplexer, and a latch. The ring oscillator generates a frequency signal. Each passive band-pass filter performs filtering on the frequency signal to pass the frequency signal or block the frequency signal. The demultiplexer receives a set of challenge bits and delivers the frequency signal to a selected passive band-pass filter among the plurality of passive band-passed filters based on the challenge bit. The latch outputs a response bit in response to the filtering performed by the selected passive band-pass filter.Type: ApplicationFiled: November 30, 2021Publication date: June 1, 2023Inventors: Dallas Lea, Yann Mignot, Marc A. Bergendahl, Alex Joseph Varghese, Sean Teehan, Andrew M. Greene, Matthew T. Shoudy
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Publication number: 20230098562Abstract: A phase change memory (PCM) cell having a mushroom configuration includes a first electrode, a heater electrically connected to the first electrode, a first projection liner electrically connected to the heater, a PCM material electrically connected to the first projection liner, a second electrode electrically connected to the PCM material, and a second projection liner electrically connected to the first projection liner and the second electrode.Type: ApplicationFiled: September 29, 2021Publication date: March 30, 2023Inventors: Kevin W. Brew, Timothy Mathew Philip, Andrew Herbert Simon, Matthew T. Shoudy, Injo Ok
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Patent number: 11164776Abstract: A method includes forming a metallic interconnect structure on a semiconductor substrate where the metallic interconnect structure comprises a plurality of metal lines with adjacent metal lines separated by a gap therebetween. The method further includes selectively depositing a first low-k dielectric material onto the semiconductor substrate and onto exposed surfaces of the metal lines of the metallic interconnect structure to form a barrier on at least the metal lines. The barrier is configured to minimize oxidation and diffusion of metal of the metal lines. The method also includes depositing a flowable second low-k dielectric material onto the semiconductor substrate to form a dielectric layer encapsulating the barrier and the metallic interconnect structure.Type: GrantFiled: September 30, 2019Date of Patent: November 2, 2021Assignee: International Business Machines CorporationInventors: Son Nguyen, Takeshi Nogami, Thomas Jasper Haigh, Jr., Cornelius Brown Peethala, Matthew T. Shoudy
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Publication number: 20210151351Abstract: Semiconductor devices and methods for forming semiconductor devices include opening at least one contact via through a sacrificial material down to contacts. Sides of the at least one contact via are lined by selectively depositing a barrier on the sacrificial material, the barrier extending along sidewalls of the at least one contact via from a top surface of the sacrificial material down to a bottom surface of the sacrificial material proximal to the contacts such that the contacts remain exposed. A conductive material is deposited in the at least one contact via down to the contacts to form stacked contacts having the hard mask on sides thereof. The sacrificial material is removed.Type: ApplicationFiled: December 29, 2020Publication date: May 20, 2021Inventors: Alex Joseph Varghese, Marc A. Bergendahl, Andrew M. Greene, Dallas Lea, Matthew T. Shoudy, Yann Mignot, Ekmini A. De Silva, Gangadhara Raja Muthinti
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Publication number: 20210098292Abstract: A method includes forming a metallic interconnect structure on a semiconductor substrate where the metallic interconnect structure comprises a plurality of metal lines with adjacent metal lines separated by a gap therebetween. The method further includes selectively depositing a first low-k dielectric material onto the semiconductor substrate and onto exposed surfaces of the metal lines of the metal interconnect structure to form a barrier on at least the metal lines. The barrier is configured to minimize oxidation and diffusion of metal of the metal lines. The method also includes depositing a flowable second low-k dielectric material onto the semiconductor structure to form a dielectric layer encapsulating the barrier and the metallic interconnect structure.Type: ApplicationFiled: September 30, 2019Publication date: April 1, 2021Inventors: Son Nguyen, Takeshi Nogami, Thomas Jasper Haigh, JR., Cornelius Brown Peethala, Matthew T. Shoudy
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Patent number: 10923401Abstract: Embodiments of the present invention are directed to techniques for providing a gate cut critical dimension (CD) shrink and active gate defect healing using selective deposition. The selective silicon on silicon deposition described herein effectively shrinks the gate cut CD to below lithographic limits and repairs any neighboring active gate damage resulting from a processing window misalignment by refilling the inadvertently removed sacrificial material. In a non-limiting embodiment of the invention, a sacrificial gate is formed over a shallow trench isolation region. A portion of the sacrificial gate is removed to expose a surface of the shallow trench isolation region. A semiconductor material is selectively deposited on exposed sidewalls of the sacrificial gate. A gate cut dielectric is formed on a portion of the shallow trench isolation between sidewalls of the semiconductor material.Type: GrantFiled: October 26, 2018Date of Patent: February 16, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Andrew Greene, Marc Bergendahl, Ekmini A. De Silva, Alex Joseph Varghese, Yann Mignot, Matthew T. Shoudy, Gangadhara Raja Muthinti, Dallas Lea
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Patent number: 10903111Abstract: Semiconductor devices and methods for forming semiconductor devices include opening at least one contact via through a sacrificial material down to contacts. Sides of the at least one contact via are lined by selectively depositing a barrier on the sacrificial material, the barrier extending along sidewalls of the at least one contact via from a top surface of the sacrificial material down to a bottom surface of the sacrificial material proximal to the contacts such that the contacts remain exposed. A conductive material is deposited in the at least one contact via down to the contacts to form stacked contacts having the hard mask on sides thereof. The sacrificial material is removed.Type: GrantFiled: March 20, 2019Date of Patent: January 26, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alex Joseph Varghese, Marc A. Bergendahl, Andrew M. Greene, Dallas Lea, Matthew T. Shoudy, Yann Mignot, Ekmini A. De Silva, Gangadhara Raja Muthinti
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Publication number: 20200388531Abstract: Embodiments of the invention include a method of forming a multi-layer integrated circuit (IC) structure that includes a forming a first IC layer above the substrate, wherein the first IC layer includes a network of interconnect structures, wherein the network of interconnect structures is configured to communicatively couple electronic devices of the IC. A second IC layer is formed over the first IC layer. The second IC layer is implanted with a predetermined ion implantation dose, maintained at a predetermined temperature, and further exposed to electromagnetic radiation from an energy source. The second IC layer is configured to, based at least in part of being exposed to the ion implantation and the electromagnetic radiation, experience changes in the chemical composition of the second IC layer and transform the second IC layer.Type: ApplicationFiled: June 4, 2019Publication date: December 10, 2020Inventors: Devika Sil, Matthew T. Shoudy, Oleg Gluschenkov, Benjamin D. Briggs, Danielle Durrant, Yasir Sulehria
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Publication number: 20200303246Abstract: Semiconductor devices and methods for forming semiconductor devices include opening at least one contact via through a sacrificial material down to contacts. Sides of the at least one contact via are lined by selectively depositing a barrier on the sacrificial material, the barrier extending along sidewalls of the at least one contact via from a top surface of the sacrificial material down to a bottom surface of the sacrificial material proximal to the contacts such that the contacts remain exposed. A conductive material is deposited in the at least one contact via down to the contacts to form stacked contacts having the hard mask on sides thereof. The sacrificial material is removed.Type: ApplicationFiled: March 20, 2019Publication date: September 24, 2020Inventors: Alex Joseph Varghese, Marc A. Bergendahl, Andrew M. Greene, Dallas Lea, Matthew T. Shoudy, Yann Mignot, Ekmini A. De Silva, Gangadhara Raja Muthinti
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Publication number: 20200135575Abstract: Embodiments of the present invention are directed to techniques for providing a gate cut critical dimension (CD) shrink and active gate defect healing using selective deposition. The selective silicon on silicon deposition described herein effectively shrinks the gate cut CD to below lithographic limits and repairs any neighboring active gate damage resulting from a processing window misalignment by refilling the inadvertently removed sacrificial material. In a non-limiting embodiment of the invention, a sacrificial gate is formed over a shallow trench isolation region. A portion of the sacrificial gate is removed to expose a surface of the shallow trench isolation region. A semiconductor material is selectively deposited on exposed sidewalls of the sacrificial gate. A gate cut dielectric is formed on a portion of the shallow trench isolation between sidewalls of the semiconductor material.Type: ApplicationFiled: October 26, 2018Publication date: April 30, 2020Inventors: Andrew Greene, Marc Bergendahl, Ekmini A. De Silva, Alex Joseph Varghese, Yann MIGNOT, Matthew T. Shoudy, GANGADHARA RAJA MUTHINTI, DALLAS LEA
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Patent number: 9640514Abstract: A bonding material stack for wafer-to-wafer bonding is provided. The bonding material stack may include a plurality of layers each including boron and nitrogen. In one embodiment, the plurality of layers may include: a first boron oxynitride layer for adhering to a wafer; a boron nitride layer over the first boron oxynitride layer; a second boron oxynitride layer over the boron nitride layer; and a silicon-containing boron oxynitride layer over the second boron oxynitride layer.Type: GrantFiled: March 29, 2016Date of Patent: May 2, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Wei Lin, Troy L. Graves-Abe, Donald F. Canaperi, Spyridon Skordas, Matthew T. Shoudy, Binglin Miao, Raghuveer R. Patlolla, Sanjay C. Mehta
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Patent number: 9607825Abstract: Embodiments of the present invention provide hydrogen-free dielectric films and methods of fabrication. A hydrogen-free precursor, such as tetraisocyanatosilane, and hydrogen-free reactants, such as nitrogen, oxygen (O2/O3) and nitrous oxide are used with chemical vapor deposition processes (PECVD, thermal CVD, SACVD, HDP CVD, and PE and Thermal ALD) to create hydrogen-free dielectric films. In some embodiments, there are multilayer dielectric films with sublayers of various materials such as silicon oxide, silicon nitride, and silicon oxynitride. In embodiments, the hydrogen-free reactants may include Tetra Isocyanato Silane, along with a hydrogen-free gas including, but not limited to, N2, O2, O3, N2O, CO2, CO and a combination thereof of these H-Free gases. Plasma may be used to enhance the reaction between the TICS and the other H-free gasses. The plasma may be controlled during film deposition to achieve variable density within each sublayer of the films.Type: GrantFiled: April 8, 2014Date of Patent: March 28, 2017Assignee: International Business Machines CorporationInventors: Donald Francis Canaperi, Alfred Grill, Sanjay C. Mehta, Son Van Nguyen, Deepika Priyadarshini, Hosadurga Shobha, Matthew T. Shoudy
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Patent number: 9558934Abstract: Embodiments of the present invention provide hydrogen-free dielectric films and methods of fabrication. A hydrogen-free precursor, such as tetraisocyanatosilane, and hydrogen-free reactants, such as nitrogen, oxygen (O2/O3) and nitrous oxide are used with chemical vapor deposition processes (PECVD, thermal CVD, SACVD, HDP CVD, and PE and Thermal ALD) to create hydrogen-free dielectric films. In some embodiments, there are multilayer dielectric films with sublayers of various materials such as silicon oxide, silicon nitride, and silicon oxynitride. In embodiments, the hydrogen-free reactants may include Tetra Isocyanato Silane, along with a hydrogen-free gas including, but not limited to, N2, O2, O3, N2O, CO2, CO and a combination thereof of these H-Free gases. Plasma may be used to enhance the reaction between the TICS and the other H-free gasses. The plasma may be controlled during film deposition to achieve variable density within each sublayer of the films.Type: GrantFiled: October 28, 2015Date of Patent: January 31, 2017Assignee: International Business Machines CorporationInventors: Donald Francis Canaperi, Alfred Grill, Sanjay C. Mehta, Son Van Nguyen, Deepika Priyadarshini, Hosadurga Shobha, Matthew T. Shoudy
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Patent number: 9558935Abstract: Embodiments of the present invention provide hydrogen-free dielectric films and methods of fabrication. A hydrogen-free precursor, such as tetraisocyanatosilane, and hydrogen-free reactants, such as nitrogen, oxygen (O2/O3) and nitrous oxide are used with chemical vapor deposition processes (PECVD, thermal CVD, SACVD, HDP CVD, and PE and Thermal ALD) to create hydrogen-free dielectric films. In some embodiments, there are multilayer dielectric films with sublayers of various materials such as silicon oxide, silicon nitride, and silicon oxynitride. In embodiments, the hydrogen-free reactants may include Tetra Isocyanato Silane, along with a hydrogen-free gas including, but not limited to, N2, O2, O3, N2O, CO2, CO and a combination thereof of these H-Free gases. Plasma may be used to enhance the reaction between the TICS and the other H-free gasses. The plasma may be controlled during film deposition to achieve variable density within each sublayer of the films.Type: GrantFiled: October 29, 2015Date of Patent: January 31, 2017Assignee: International Business Machines CorporationInventors: Donald Francis Canaperi, Alfred Grill, Sanjay C. Mehta, Son Van Nguyen, Deepika Priyadarshini, Hosadurga Shobha, Matthew T. Shoudy
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Patent number: 9536733Abstract: Embodiments of the present invention provide hydrogen-free dielectric films and methods of fabrication. A hydrogen-free precursor, such as tetraisocyanatosilane, and hydrogen-free reactants, such as nitrogen, oxygen (O2/O3) and nitrous oxide are used with chemical vapor deposition processes (PECVD, thermal CVD, SACVD, HDP CVD, and PE and Thermal ALD) to create hydrogen-free dielectric films. In some embodiments, there are multilayer dielectric films with sublayers of various materials such as silicon oxide, silicon nitride, and silicon oxynitride. In embodiments, the hydrogen-free reactants may include Tetra Isocyanato Silane, along with a hydrogen-free gas including, but not limited to, N2, O2, O3, N2O, CO2, CO and a combination thereof of these H-Free gases. Plasma may be used to enhance the reaction between the TICS and the other H-free gasses. The plasma may be controlled during film deposition to achieve variable density within each sublayer of the films.Type: GrantFiled: October 29, 2015Date of Patent: January 3, 2017Assignee: International Business Machines CorporationInventors: Donald Francis Canaperi, Alfred Grill, Sanjay C. Mehta, Son Van Nguyen, Deepika Priyadarshini, Hosadurga Shobha, Matthew T. Shoudy
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Patent number: 9449812Abstract: Embodiments of the present invention provide hydrogen-free dielectric films and methods of fabrication. A hydrogen-free precursor, such as tetraisocyanatosilane, and hydrogen-free reactants, such as nitrogen, oxygen (O2/O3) and nitrous oxide are used with chemical vapor deposition processes (PECVD, thermal CVD, SACVD, HDP CVD, and PE and Thermal ALD) to create hydrogen-free dielectric films. In some embodiments, there are multilayer dielectric films with sublayers of various materials such as silicon oxide, silicon nitride, and silicon oxynitride. In embodiments, the hydrogen-free reactants may include Tetra Isocyanato Silane, along with a hydrogen-free gas including, but not limited to, N2, O2, O3, N2O, CO2, CO and a combination thereof of these H-Free gases. Plasma may be used to enhance the reaction between the TICS and the other H-free gasses. The plasma may be controlled during film deposition to achieve variable density within each sublayer of the films.Type: GrantFiled: November 2, 2015Date of Patent: September 20, 2016Assignee: International Business Machines CorporationInventors: Donald Francis Canaperi, Alfred Grill, Sanjay C. Mehta, Son Van Nguyen, Deepika Priyadarshini, Hosadurga Shobha, Matthew T. Shoudy
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Patent number: 9312224Abstract: A porous low k dielectric material containing atoms of at least Si, C, N and H (C and/or O may also be present) is used to provide an interconnect structure having reduced BEOL capacitance and resistance. The porous low k dielectric material is used as an interconnect dielectric material in which at least one interconnect metal-containing structure is embedded therein. The porous low k dielectric material has metal diffusion barrier properties due to the presence of nitrogen as an elemental constituent of the porous low k dielectric material. As such, the porous low k dielectric material can eliminate the need of a diffusion barrier liner, or reduce the thickness of the diffusion barrier liner that is typically formed between an interconnect dielectric material and the embedded interconnect metal structure.Type: GrantFiled: December 11, 2014Date of Patent: April 12, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Donald F. Canaperi, Alfred Grill, Thomas J. Haigh, Son V. Nguyen, Takeshi Nogami, Deepika Priyadarshini, Hosadurga Shobha, Matthew T. Shoudy
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Publication number: 20160064509Abstract: Embodiments of the present invention provide hydrogen-free dielectric films and methods of fabrication. A hydrogen-free precursor, such as tetraisocyanatosilane, and hydrogen-free reactants, such as nitrogen, oxygen (O2/O3) and nitrous oxide are used with chemical vapor deposition processes (PECVD, thermal CVD, SACVD, HDP CVD, and PE and Thermal ALD) to create hydrogen-free dielectric films. In some embodiments, there are multilayer dielectric films with sublayers of various materials such as silicon oxide, silicon nitride, and silicon oxynitride. In embodiments, the hydrogen-free reactants may include Tetra Isocyanato Silane, along with a hydrogen-free gas including, but not limited to, N2, O2, O3, N2O, CO2, CO and a combination thereof of these H-Free gases. Plasma may be used to enhance the reaction between the TICS and the other H-free gasses. The plasma may be controlled during film deposition to achieve variable density within each sublayer of the films.Type: ApplicationFiled: October 29, 2015Publication date: March 3, 2016Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Donald Francis Canaperi, Alfred Grill, Sanjay C. Mehta, Son Van Nguyen, Deepika Priyadarshini, Hosadurga Shobha, Matthew T. Shoudy