Abstract: A semiconductor device manufacturing system is introduced. The system includes a carrier wafer, a first electrode layer disposed on the carrier wafer, a piezoelectric layer disposed on the first electrode layer, and a second electrode layer disposed on the piezoelectric layer. In addition, the system includes a device wafer having a bonding layer disposed on a surface of the device wafer, and a power source having a first terminal and a second terminal. The device wafer is bonded to the carrier wafer through the bonding layer, the first electrode layer, the piezoelectric layer, and the second electrode layer. The second electrode layer is configured to separate from the first electrode layer upon application of a bias voltage to the first and second electrode layers, and the device wafer is configured to debond from the carrier wafer through delaminating the piezoelectric layer from the first or second electrode layer.

Abstract: Electrolytic methods for carrier wafer separation are disclosed herein. In some embodiments, the method includes depositing a coating on a carrier wafer. The coating can include a first electrode layer, a second electrode layer, and a metal oxide layer between the first and second electrode layers. The method can further include attaching a device wafer to the coating, processing the device wafer, and applying a bias voltage to the first and second electrode layers. Applying the bias voltage can separate the device wafer from the carrier wafer.

Abstract: Memory devices, such as three-dimensional cross-point memory devices, and methods of manufacturing such devices are addressed. Multiple methods of manufacturing such memory devices are described to provide improved protection of replacement gate structures, such as word lines and in some examples, word line liners. These include processing flows which form one or more additional barrier structures between structures subject to at least partial removal during the processing flow; wherein some portion of the additional barrier structure(s) will remain at the end of manufacturing.

Abstract: Methods, systems, and devices for memory cell formation in pier and pillar architectures are described. A stack of materials including alternating layers of nitride and oxide may be formed, and a plurality of columns of a third material may be formed in the stack. The third material may be recessed (e.g., laterally) filled with at least an electrode liner and a metal material. Portions of the nitride material and an oxide liner that are adjacent to the third material may be removed, and a second electrode liner may be formed (e.g., in the regions from which the nitride material and oxide liner were removed). Memory cells may be formed after removing the portion of the nitride material and oxide liner such that the cells are in contact with the second electrode liner.

Abstract: Memory devices, such as three-dimensional cross-point memory devices, and methods of manufacturing such devices are addressed. Some known methods for manufacturing such memory devices rely upon sacrificial materials which are at least partially exhumed during processing to complete the memory devices. Etch chemistries for removing such sacrificial materials may risk of removing or damaging materials or structures to the detriment of the process. An example method of avoiding damage to vertically extending conductive materials uses protective plugs above the conductive structures to isolate the conductive structures while other structures are exhumed.

Abstract: Integrated circuitry comprises a stack comprising vertically-alternating insulative tiers and conductive tiers that extend from an array region into a stair-step region. Individual treads of the stairs comprise conductive material of one of the conductive tiers. A conductive via extends from directly above, through, and to directly below one of the individual treads to a bottom of the stack. The conductive via comprises conductor material that is directly electrically coupled to conductive material of the target conductive tier of the one individual tread. The conductive material of the target conductive tier of the one individual tread is not directly above the conductive material that is in the conductive tier that is immediately-below the one individual tread. Other embodiments, including method, are disclosed.

Abstract: A semiconductor die assembly is introduced in this disclosure. The semiconductor die assembly includes one or more semiconductor dies, a dielectric layer disposed under a bottom surface of the one or more semiconductor dies, and metal fragments or a metal layer disposed under the dielectric layer, wherein metal-OH bonds or metal-O—Si—OH bonds are disposed on a bottom surface of the dielectric layer. Alternatively, the semiconductor die assembly includes one or more semiconductor dies, a metal layer disposed under a bottom surface of the one or more semiconductor dies, and a metal oxidation layer disposed under the dielectric layer, wherein the metal oxidation layer comprises metal-OH bonds or metal-O—Si—OH bonds.

Abstract: Integrated circuitry comprises a stack comprising vertically-alternating insulative tiers and conductive tiers that extend from an array region into a stair-step region. The stair-step region comprises a flight of stairs that comprise treads, with individual of the treads comprising a target conductive tier. A conductive via extends from directly above, through, and to directly below one of the individual treads to a bottom of the stack. The conductive via comprises conductor material that is directly electrically coupled to the conductive material that is in the target conductive tier of the one individual tread. The conductor material is in the target conductive tier directly above and directly below the conductive material that is in the target conductive tier. Other embodiments, including method, are disclosed.

Abstract: Methods, systems, and devices for memory architectures with replacement gate through piers are described. A memory architecture with relatively uniform memory cell thickness may be formed by forming a stack of materials including alternating layers of sacrificial material and dielectric material. The processing steps may include forming piers and forming cavities for pillars through the stack of materials. The pillars and electrodes may be formed within the cavities, and a subset of the piers may be removed. The layers of sacrificial material may be removed. A protective liner may be deposited around the electrodes and the remaining piers before depositing layers of metal in place of the sacrificial material. The cavities exposed by removing the subset of piers may be filled with new piers. The remaining piers are removed, and memory cells may be formed between the pillars and the electrodes. Then the removed piers are replaced.

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating first and second levels. A panel extends through the stack. The first levels have proximal regions adjacent the panel, and have distal regions further from the panel than the proximal regions. The distal regions include conductive structures. The conductive structures have a first thickness. The proximal regions include insulative structures. The insulative structures have a second thickness at least about as large as the first thickness. Some embodiments include methods of forming integrated assemblies.

Abstract: A microelectronic device comprises a stack structure overlying a source tier. The stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. The microelectronic device comprises a staircase structure within the stack structure and having steps comprising lateral edges of the tiers, support structures vertically extending through the stack structure and within a horizontal area of the staircase structure, and conductive contacts vertically extending through the stack structure and horizontally neighboring the support structures within the horizontal area of the staircase structure. Each of the conductive contacts has a horizontally projecting portion in contact with one of the conductive structures of the stack structure at one of the steps of the staircase structure. Related memory devices, electronic systems, and methods of forming the microelectronic devices are also described.

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating first and second levels. A panel extends through the stack. The first levels have proximal regions adjacent the panel, and have distal regions further from the panel than the proximal regions. The distal regions include conductive structures. The conductive structures have a first thickness. The proximal regions include insulative structures. The insulative structures have a second thickness at least about as large as the first thickness. Some embodiments include methods of forming integrated assemblies.

Abstract: A microelectronic device comprises a stack structure overlying a source tier. The stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. The microelectronic device comprises a staircase structure within the stack structure and having steps comprising lateral edges of the tiers, support structures vertically extending through the stack structure and within a horizontal area of the staircase structure, and conductive contacts vertically extending through the stack structure and horizontally neighboring the support structures within the horizontal area of the staircase structure. Each of the conductive contacts has a horizontally projecting portion in contact with one of the conductive structures of the stack structure at one of the steps of the staircase structure. Related memory devices, electronic systems, and methods of forming the microelectronic devices are also described.

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative and conductive levels. The conductive levels have terminal regions and nonterminal regions. The terminal regions are vertically thicker than the nonterminal regions. Channel material extends vertically through the stack. Tunneling material is adjacent the channel material. Charge-storage material is adjacent the tunneling material. High-k dielectric material is between the charge-storage material and the terminal regions of the conductive levels. The insulative levels have carbon-containing first regions between the terminal regions of neighboring conductive levels, and have second regions between the nonterminal regions of the neighboring conductive levels. Some embodiments include methods of forming integrated assemblies.

Abstract: A microelectronic device comprises a stack structure overlying a source tier. The stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. The microelectronic device comprises a staircase structure within the stack structure and having steps comprising lateral edges of the tiers, support structures vertically extending through the stack structure and within a horizontal area of the staircase structure, and conductive contacts vertically extending through the stack structure and horizontally neighboring the support structures within the horizontal area of the staircase structure. Each of the conductive contacts has a horizontally projecting portion in contact with one of the conductive structures of the stack structure at one of the steps of the staircase structure. Related memory devices, electronic systems, and methods of forming the microelectronic devices are also described.

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating first and second levels. A panel extends through the stack. The first levels have proximal regions adjacent the panel, and have distal regions further from the panel than the proximal regions. The distal regions include conductive structures. The conductive structures have a first thickness. The proximal regions include insulative structures. The insulative structures have a second thickness at least about as large as the first thickness. Some embodiments include methods of forming integrated assemblies.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. The second tiers comprise doped silicon dioxide and the first tiers comprise a material other than doped silicon dioxide. The stack comprises laterally-spaced memory-block regions. Channel-material-string constructions extend through the first tiers and the second tiers in the memory-block regions. The doped silicon dioxide that is in the second tiers is etched selectively relative to said other material that is in the first tiers and selectively relative to and to expose an undoped silicon dioxide-comprising string of a charge-blocking material that is part of individual of the channel-material-string constructions. Structure independent of method is disclosed.

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative and conductive levels. The conductive levels have terminal regions and nonterminal regions. The terminal regions are vertically thicker than the nonterminal regions. Channel material extends vertically through the stack. Tunneling material is adjacent the channel material. Charge-storage material is adjacent the tunneling material. High-k dielectric material is between the charge-storage material and the terminal regions of the conductive levels. The insulative levels have carbon-containing first regions between the terminal regions of neighboring conductive levels, and have second regions between the nonterminal regions of the neighboring conductive levels. Some embodiments include methods of forming integrated assemblies.

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative and conductive levels. The conductive levels have terminal regions and nonterminal regions. The terminal regions are vertically thicker than the nonterminal regions. Channel material extends vertically through the stack. Tunneling material is adjacent the channel material. Charge-storage material is adjacent the tunneling material. High-k dielectric material is between the charge-storage material and the terminal regions of the conductive levels. The insulative levels have carbon-containing first regions between the terminal regions of neighboring conductive levels, and have second regions between the nonterminal regions of the neighboring conductive levels. Some embodiments include methods of forming integrated assemblies.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. The second tiers comprise doped silicon dioxide and the first tiers comprise a material other than doped silicon dioxide. The stack comprises laterally-spaced memory-block regions. Channel-material-string constructions extend through the first tiers and the second tiers in the memory-block regions. The channel-material-string constructions individually comprise a channel-material string that extends through the first tiers and the second tiers in the memory-block regions. The doped silicon dioxide that is in the second tiers is etched selectively relative to said other material that is in the first tiers and selectively relative to and to expose an undoped silicon dioxide-comprising string of a charge-blocking material that is part of individual of the channel-material-string constructions.