Patents by Inventor Matthew Tingey
Matthew Tingey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240088052Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.Type: ApplicationFiled: November 17, 2023Publication date: March 14, 2024Inventors: Bai NIE, Gang DUAN, Srinivas PIETAMBARAM, Jesse JONES, Yosuke KANAOKA, Hongxia FENG, Dingying XU, Rahul MANEPALLI, Sameer PAITAL, Kristof DARMAWIKARTA, Yonggang LI, Meizi JIAO, Chong ZHANG, Matthew TINGEY, Jung Kyu HAN, Haobo CHEN
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Patent number: 11923312Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.Type: GrantFiled: March 27, 2019Date of Patent: March 5, 2024Assignee: Intel CorporationInventors: Bai Nie, Gang Duan, Srinivas Pietambaram, Jesse Jones, Yosuke Kanaoka, Hongxia Feng, Dingying Xu, Rahul Manepalli, Sameer Paital, Kristof Darmawikarta, Yonggang Li, Meizi Jiao, Chong Zhang, Matthew Tingey, Jung Kyu Han, Haobo Chen
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Patent number: 11817349Abstract: A conductive route for an integrated circuit assembly may be formed using a sequence of etching and passivation steps through layers of conductive material, wherein the resulting structure may include a first route portion having a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, an etch stop structure on the first route portion, a second route portion on the etch stop layer, wherein the second route portion has a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, and a passivating layer abutting the at least one side surface of the second route portion.Type: GrantFiled: March 5, 2020Date of Patent: November 14, 2023Assignee: Intel CorporationInventors: Jeremy Ecton, Brandon C. Marin, Leonel Arana, Matthew Tingey, Oscar Ojeda, Hsin-Wei Wang, Suddhasattwa Nad, Srinivas Pietambaram, Gang Duan
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Publication number: 20220399150Abstract: An electronic substrate may be fabricated having a dielectric material, metal pads embedded in the dielectric material with co-planar surfaces spaced less than one tenth millimeter from each other, and a metal trace embedded in the dielectric material and attached between the metal pads, wherein a surface of the metal trace is non-co-planar with the co-planar surfaces of the metal pads at a height of less than one millimeter, and wherein sides of the metal trace are angled relative to the co-planar surfaces of the metal pads. In an embodiment of the present description, an embedded angled inductor may be formed that includes the metal trace. In an embodiment, an integrated circuit package may be formed with the electronic substrate, wherein at least one integrated circuit devices may be attached to the electronic substrate. Other embodiments are disclosed and claimed.Type: ApplicationFiled: June 15, 2021Publication date: December 15, 2022Applicant: Intel CorporationInventors: Brandon Marin, Jeremy Ecton, Suddhasattwa Nad, Matthew Tingey, Ravindranath Mahajan, Srinivas Pietambaram
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Publication number: 20210375746Abstract: Processes and structures resulting therefrom for the improvement of high speed signaling integrity in electronic substrates of integrated circuit packages, which is achieved with the formation of airgap structures within dielectric material(s) between adjacent conductive routes that transmit/receive electrical signals, wherein the airgap structures decrease the capacitance and/or decrease the insertion losses in the dielectric material used to form the electronic substrates.Type: ApplicationFiled: May 27, 2020Publication date: December 2, 2021Applicant: INTEL CORPORATIONInventors: Hongxia Feng, Jeremy Ecton, Aleksandar Aleksov, Haobo Chen, Xiaoying Guo, Brandon C. Marin, Zhiguo Qian, Daryl Purcell, Leonel Arana, Matthew Tingey
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Publication number: 20210318612Abstract: The present disclosure is directed to a patterning process that includes providing a composite dry film resist on a surface, in which the composite dry film resist includes a base film, a barrier layer and a resist layer, in which the base film is disposed over the barrier layer and the barrier layer is disposed over the resist layer. In another aspect, the patterning process includes removing the base film from the barrier layer and exposing the barrier layer to form an exposure precursor, which has a first area and a second area, further exposing the first area of the exposure precursor to electromagnetic irradiation, which passes through the barrier layer and the resist layer in the exposed first area becomes water-insoluble, and removing the barrier layer and the unexposed second area to form a pattern template.Type: ApplicationFiled: June 24, 2021Publication date: October 14, 2021Inventors: Hongxia FENG, Changhua LIU, Bohan SHAN, Dingying XU, Leonel ARANA, Manuel GADOGBE, Matthew TINGEY, Julianne TROIANO
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Publication number: 20210280463Abstract: A conductive route for an integrated circuit assembly may be formed using a sequence of etching and passivation steps through layers of conductive material, wherein the resulting structure may include a first route portion having a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, an etch stop structure on the first route portion, a second route portion on the etch stop layer, wherein the second route portion has a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, and a passivating layer abutting the at least one side surface of the second route portion.Type: ApplicationFiled: March 5, 2020Publication date: September 9, 2021Applicant: INTEL CORPORATIONInventors: Jeremy Ecton, Brandon C. Marin, Leonel Arana, Matthew Tingey, Oscar Ojeda, Hsin-Wei Wang, Suddhasattwa Nad, Srinivas Pietambaram, Gang Duan
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Publication number: 20200312771Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.Type: ApplicationFiled: March 27, 2019Publication date: October 1, 2020Inventors: Bai NIE, Gang DUAN, Srinivas PIETAMBARAM, Jesse JONES, Yosuke KANAOKA, Hongxia FENG, Dingying XU, Rahul MANEPALLI, Sameer PAITAL, Kristof DARMAWIKARTA, Yonggang LI, Meizi JIAO, Chong ZHANG, Matthew TINGEY, Jung Kyu HAN, Haobo CHEN
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Patent number: 8233210Abstract: Embodiments of systems and methods for providing a hybrid illumination aperture in optical lithography are generally described herein. Other embodiments may be described and claimed.Type: GrantFiled: December 30, 2008Date of Patent: July 31, 2012Assignee: Intel CorporationInventors: Charles Wallace, Matthew Tingey, Swaminathan Sivakumar
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Patent number: 7915171Abstract: Double patterning techniques and structures are generally described. In one example, a method includes depositing a first photoresist to a semiconductor substrate, forming a first integrated circuit (IC) pattern in the first photoresist, the first IC pattern comprising one or more trench structures, protecting the first IC pattern in the first photoresist from actions that form a second IC pattern in a second photoresist, depositing the second photoresist to the first IC pattern, and forming the second IC pattern in the second photoresist, the second IC pattern comprising one or more structures that are sufficiently close to the one or more trench structures of the first IC pattern to cause scumming of the second photoresist in the one or more trench structures of the first IC pattern.Type: GrantFiled: April 29, 2008Date of Patent: March 29, 2011Assignee: Intel CorporationInventors: Charles H. Wallace, Matthew Tingey, Swaminathan Sivakumar
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Publication number: 20100165317Abstract: Embodiments of systems and methods for providing a hybrid illumination aperture in optical lithography are generally described herein. Other embodiments may be described and claimed.Type: ApplicationFiled: December 30, 2008Publication date: July 1, 2010Inventors: Charles Wallace, Matthew Tingey, Swaminathan Sivakumar
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Publication number: 20090267175Abstract: Double patterning techniques and structures are generally described. In one example, a method includes depositing a first photoresist to a semiconductor substrate, forming a first integrated circuit (IC) pattern in the first photoresist, the first IC pattern comprising one or more trench structures, protecting the first IC pattern in the first photoresist from actions that form a second IC pattern in a second photoresist, depositing the second photoresist to the first IC pattern, and forming the second IC pattern in the second photoresist, the second IC pattern comprising one or more structures that are sufficiently close to the one or more trench structures of the first IC pattern to cause scumming of the second photoresist in the one or more trench structures of the first IC pattern.Type: ApplicationFiled: April 29, 2008Publication date: October 29, 2009Inventors: Charles H. Wallace, Matthew Tingey, Swaminathan Sivakumar
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Publication number: 20050079486Abstract: The present invention provides methods, devices and kits for detecting a ligand. The methods involve capturing a ligand from a sample with an affinity substrate that includes a receptor for a ligand, transferring captured ligand to a detection surface and detecting the ligand on the detection surface with a liquid crystal. Accordingly, the capture step is decoupled from the detection step.Type: ApplicationFiled: September 23, 2004Publication date: April 14, 2005Inventors: Nicholas ABBOTT, Matthew TINGEY, Brian CLARE, Chang-Hyun JANG