Abstract: An extended protocol provides a serial bus with the capability of effective communications for a multimaster bus. A bus device may enter a master mode and transmit information identifying a designated recipient device on the bus. Either the master mode device or the designated recipient device may send information that identifies the master mode bus device. The master mode device may read from the designated recipient device or may write to the designated recipient device. The designated recipient device may provide an acknowledgement, data, a command, or status information may be sent back. The status information may include version information regarding the hardware, software, and/or firmware of the designated recipient device.

Abstract: Disclosed is a test method for a computer microprocessor adapted to stress the data transfer interfaces within a microprocessor. The method incorporates patterns designed to stress the interfaces and are further repeated in different widths such that interfaces of various bus widths are fully stressed. Further, the method begins with the various test patterns preloaded into memory to maximize the speed and thus the stress of the test.

Abstract: A microprocessor based system automatically detects the occurrence of certain conditions in the microprocessor. The conditions may include a determination of data corruption in the microprocessor. If a determination is made that data is corrupted, the microprocessor may be reloaded from a non-volatile memory. During a reload, a microcontroller controls the microprocessor. The non-volatile memory may be a flash memory or non-volatile random access memory.

Abstract: A microprocessor based system automatically detects the occurrence of certain conditions in the microprocessor. The conditions may include a determination of data corruption in the microprocessor. If a determination is made that data is corrupted, the microprocessor may be reloaded from a non-volatile memory. During a reload, a microcontroller controls the microprocessor. The non-volatile memory may be a flash memory or non-volatile random access memory.

Abstract: Disclosed is a test method for a computer microprocessor adapted to stress the data transfer interfaces within a microprocessor. The method incorporates patterns designed to stress the interfaces and are further repeated in different widths such that interfaces of various bus widths are fully stressed. Further, the method begins with the various test patterns preloaded into memory to maximize the speed and thus the stress of the test.

Abstract: An adapter permits bi-directional communications between a full duplex mode, two data wire serial data bus and a half duplex mode, one data wire serial data bus. Settings or preferences for the full duplex mode bus may be set by the half duplex mode bus using a command format. Processing by the adapter controller may be interrupt driven, except during the processing of the half duplex mode serial data bus, when the interrupts may be disabled.

Abstract: An extended protocol provides a serial bus with the capability of effective communications for a multimaster bus. A bus device may enter a master mode and transmit information identifying a designated recipient device on the bus. Either the master mode device or the designated recipient device may send information that identifies the master mode bus device. The master mode device may read from the designated recipient device or may write to the designated recipient device. The designated recipient device may provide an acknowledgement, data, a command, or status information may be sent back. The status information may include version information regarding the hardware, software, and/or firmware of the designated recipient device.