Patents by Inventor Matthew Turnquist
Matthew Turnquist has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11953970Abstract: A controllable voltage source (902) is coupled to a microelectronic circuit (901) for providing an operating voltage. Said microelectronic circuit (901) is adaptive, so its performance is at least partly configurable by value of said operating voltage. The operating voltage is regulated into conformity with a target value. Reregulating said operating voltage into conformity with a new target value involves a time constant. On a processing path a first register circuit (502) comprises a data input coupled to an output of a preceding first logic unit (501). The microelectronic circuit (901) responds to a digital value at said data input changing later than an allowable time limit by generating a timing event observation (TEO) signal. The allowable time limit is defined by at least one triggering edge of at least one triggering signal coupled to the first register circuit (502). The system uses said TEO signal to trigger an increase in said operating voltage faster than said time constant.Type: GrantFiled: January 23, 2019Date of Patent: April 9, 2024Assignee: Minima Processor OyInventors: Matthew Turnquist, Navneet Gupta, Lauri Koskinen, Tuomas Hollman
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Publication number: 20220121268Abstract: A controllable voltage source (902) is coupled to a microelectronic circuit (901) for providing an operating voltage. Said microelectronic circuit (901) is adaptive, so its performance is at least partly configurable by value of said operating voltage. The operating voltage is regulated into conformity with a target value. Reregulating said operating voltage into conformity with a new target value involves a time constant. On a processing path a first register circuit (502) comprises a data input coupled to an output of a preceding first logic unit (501). The microelectronic circuit (901) responds to a digital value at said data input changing later than an allowable time limit by generating a timing event observation (TEO) signal. The allowable time limit is defined by at least one triggering edge of at least one triggering signal coupled to the first register circuit (502). The system uses said TEO signal to trigger an increase in said operating voltage faster than said time constant.Type: ApplicationFiled: January 23, 2019Publication date: April 21, 2022Inventors: Matthew TURNQUIST, Navneet GUPTA, Lauri KOSKINEN, Tuomas HOLLMAN
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Publication number: 20210143808Abstract: It is an objective to provide timing event detection. According to a first aspect, a device, comprises: a clocked conditional buffer configured to set an output of the clocked conditional buffer to a first state during a non-detection period; the clocked conditional buffer further configured to toggle the output from the first state to the second state during a detection period, wherein the toggling being enabled by either one of the two states; and the clocked conditional buffer further configured to guarantee that the output is toggling only to one direction during the detection period. This may prevent false event detections. Furthermore, with respect to a timing point of view, one is able to operate without pulses, where pulse width may be difficult to manage in low voltages.Type: ApplicationFiled: June 22, 2017Publication date: May 13, 2021Applicant: Minima Processor OyInventors: Ari PAASIO, Matthew TURNQUIST, Lauri KOSKINEN
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Patent number: 10924098Abstract: A sequential circuit with timing event detection is disclosed. The sequential circuit has an input that is asserted to the output during the second clock phase of a two phase clock signal. A timing event detector is coupled to the sequential element input to assert a timing event signal if a transition occurs at the sequential element input during the second clock phase but not to assert during the first clock phase.Type: GrantFiled: April 18, 2017Date of Patent: February 16, 2021Assignee: MINIMA PROCESSOR OYInventors: Matthew Turnquist, Ari Paasio
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Publication number: 20200099372Abstract: A sequential circuit with timing event detection is disclosed. The sequential circuit has an input that is asserted to the output during the second clock phase of a two phase clock signal. A timing event detector is coupled to the sequential element input to assert a timing event signal if a transition occurs at the sequential element input during the second clock phase but not to assert during the first clock phase.Type: ApplicationFiled: April 18, 2017Publication date: March 26, 2020Applicant: MINIMA PROCESSOR OYInventors: Matthew TURNQUIST, Ari PAASIO
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Patent number: 10469084Abstract: A level shifter comprises a first control switch (207) for connecting an output terminal to a first supply voltage (VDDH) to set an output signal to be high, and a second control switch (208) for connecting the output terminal to a signal ground (GND) to set the output signal to be low. The level shifter comprises a pre-charging switch (210) for connecting the output terminal to the first supply voltage, and an input gate circuit (211) for controlling an ability of an input signal to control the second control switch. The level shifter comprises a keeper circuit (212) for controlling the first control switch based on the output signal. The first control switch is controlled with the first supply voltage when the output signal is low, and with a second supply voltage that is between the first supply voltage and the signal ground when the output signal is high.Type: GrantFiled: June 22, 2017Date of Patent: November 5, 2019Assignee: Minima Processor OyInventors: Ari Paasio, Lauri Koskinen, Matthew Turnquist
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Patent number: 10114442Abstract: A control system for controlling an operating voltage of an electronic device is presented. The electronic device includes a timing event detector responsive to timing events, such as errors, related to operation of the electronic device. The control system includes a controller for decreasing the operating voltage when the rate of timing events is below a target level and for increasing the operating voltage when the rate of timing events exceeds the target level to search for a threshold voltage that is the smallest operating voltage at which the rate of timing events is substantially at the target level. The control system further includes a controllable clock signal generator for producing a clock signal for operating the electronic device so that the clock frequency is according to an increasing function of the operating voltage. Thus, it is possible to find a voltage-frequency operating point where the energy consumption is minimized.Type: GrantFiled: December 16, 2016Date of Patent: October 30, 2018Assignee: MINIMA PROCESSOR OYInventors: Matthew Turnquist, Lauri Koskinen, Markus Hiienkari, Jani Mäkipää
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Patent number: 10013295Abstract: There is provided an apparatus comprising thresholding means adapted to check if an average frequency of occurrence of timing violations is outside a range; and controlling means adapted to control at least one of a clock frequency, a processing, a heat generation, a bias voltage, a current, and a temperature in a direction to bring the average frequency of occurrence of timing violations into the range if the average frequency of occurrence of timing violations is outside the range.Type: GrantFiled: June 17, 2014Date of Patent: July 3, 2018Assignee: MINIMA PROCESSOR OYInventors: Jani Mäkipää, Lauri Koskinen, Matthew Turnquist, Markus Hiienkari
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Publication number: 20170373691Abstract: A level shifter comprises a first control switch (207) for connecting an output terminal to a first supply voltage (VDDH) to set an output signal to be high, and a second control switch (208) for connecting the output terminal to a signal ground (GND) to set the output signal to be low. The level shifter comprises a pre-charging switch (210) for connecting the output terminal to the first supply voltage, and an input gate circuit (211) for controlling an ability of an input signal to control the second control switch. The level shifter comprises a keeper circuit (212) for controlling the first control switch based on the output signal. The first control switch is controlled with the first supply voltage when the output signal is low, and with a second supply voltage that is between the first supply voltage and the signal ground when the output signal is high.Type: ApplicationFiled: June 22, 2017Publication date: December 28, 2017Inventors: Ari Paasio, Lauri Koskinen, Matthew Turnquist
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Patent number: 9838019Abstract: A field effect transistor current mode differential logic circuit comprising load transistors for converting the current output of each differential leg current to voltage output, and means for configuring the bulk of each differential leg's load transistor to be connected to the drain of the load transistor for use the logic circuit in Subthreshold Source Coupled Logic (STSCL) mode, and means for configuring the bulk of each leg load transistor to be connected to a voltage or to source of the same transistor for use in MOS current more logic (MCML) operation.Type: GrantFiled: October 20, 2011Date of Patent: December 5, 2017Assignee: Minima Processor OyInventors: Matthew Turnquist, Lauri Koskinen, Jani Mäkipää, Erkka Laulainen
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Patent number: 9774329Abstract: An apparatus, comprising a clock adapted to provide a clock signal alternating with a cycle between a first level and a second level if a timing violation is not detected; a first latch adapted to be clocked such that it passes a first signal when the clock signal is at the first level; a second combinational logic adapted to output a second signal based on the first signal passed through the first latch; a second latch adapted to be clocked such that it passes the second signal when the clock signal is at the second level; a detecting means adapted to detect the timing violation of at least one of the first signal and of the second signal; a time stretching means adapted to stretch, if the timing violation is detected, the clock such that the clock alternates between the first level and the second level with a delay.Type: GrantFiled: October 2, 2014Date of Patent: September 26, 2017Assignee: Minima Processor OyInventors: Jani Mäkipää, Lauri Koskinen, Matthew Turnquist, Markus Hiienkari
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Publication number: 20160241241Abstract: An apparatus, comprising a clock adapted to provide a clock signal alternating with a cycle between a first level and a second level if a timing violation is not detected; a first latch adapted to be clocked such that it passes a first signal when the clock signal is at the first level; a second combinational logic adapted to output a second signal based on the first signal passed through the first latch; a second latch adapted to be clocked such that it passes the second signal when the clock signal is at the second level; a detecting means adapted to detect the timing violation of at least one of the first signal and of the second signal; a time stretching means adapted to stretch, if the timing violation is detected, the clock such that the clock alternates between the first level and the second level with a delay.Type: ApplicationFiled: October 2, 2014Publication date: August 18, 2016Inventors: Jani MÄKIPÄÄ, Lauri KOSKINEN, Matthew TURNQUIST, Markus HIENKARI
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Patent number: 9397662Abstract: A sequential circuit with transition error detector including a sequential element with an input that is asserted to the output during the second clock phase of a two phase clock signal, a transition error detector coupled to the sequential element input to assert an error signal if a transition occurs at the sequential element input during the second clock phase but not to assert during the first clock phase, wherein a transition error detection circuit comprises a current mode circuit as a detection circuit for transition timing error detection from signals derived from the sequential element clock signal and input signals.Type: GrantFiled: July 13, 2011Date of Patent: July 19, 2016Assignee: Aalto University FoundationInventors: Matthew Turnquist, Lauri Koskinen, Jani Mäkipää, Erkka Laulainen
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Publication number: 20160147588Abstract: There is provided an apparatus comprising thresholding means adapted to check if an average frequency of occurrence of timing violations is outside a range; and controlling means adapted to control at least one of a clock frequency, a processing, a heat generation, a bias voltage, a current, and a temperature in a direction to bring the average frequency of occurrence of timing violations into the range if the average frequency of occurrence of timing violations is outside the range.Type: ApplicationFiled: June 17, 2014Publication date: May 26, 2016Inventors: Jani MÄKIPÄÄ, Lauri KOSKINEN, Matthew TURNQUIST, Markus HIJENKARI
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Publication number: 20130207690Abstract: A field effect transistor current mode differential logic circuit comprising load transistors for converting the current output of each differential leg current to voltage output, and means for configuring the bulk of each differential leg's load transistor to be connected to the drain of the load transistor for use the logic circuit in Subthreshold Source Coupled Logic (STSCL) mode, and means for configuring the bulk of each leg load transistor to be connected to a voltage or to source of the same transistor for use in MOS current more logic (MCML) operation.Type: ApplicationFiled: October 20, 2011Publication date: August 15, 2013Applicant: Aalto University FoundationInventors: Matthew Turnquist, Lauri Koskinen, Jani Mäkipää, Erkka Laulainen
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Publication number: 20130193999Abstract: A sequential circuit with transition error detector including a sequential element with an input that is asserted to the output during the second clock phase of a two phase clock signal, a transition error detector coupled to the sequential element input to assert an error signal if a transition occurs at the sequential element input during the second clock phase but not to assert during the first clock phase, wherein a transition error detection circuit comprises a current mode circuit as a detection circuit for transition timing error detection from signals derived from the sequential element clock signal and input signals.Type: ApplicationFiled: July 13, 2011Publication date: August 1, 2013Applicant: Aalto University FoundationInventors: Matthew Turnquist, Lauri Koskinen, Jani Mäkipää, Erkka Laulainen