Patents by Inventor Matthew TWAROG

Matthew TWAROG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240266301
    Abstract: An apparatus, includes a PCB, a semiconductor package that includes a substrate and a stiffener with an opening, and at least one connection component. The stiffener is disposed on a top surface of the PCB. The at least one connection component is configured to connect the PCB to the semiconductor package. The at least one connection component may include another PCB that is disposed on the substrate within the opening of the stiffener and on the PCB. The at least one connection component may include an array of connectors that are disposed on the substrate within the opening of the stiffener, and may include a socket disposed on the PCB. The at least one connection component may include a BGA that is disposed on the substrate within the opening of the stiffener and on the PCB and on a pedestal portion of a surface of the PCB.
    Type: Application
    Filed: February 7, 2023
    Publication date: August 8, 2024
    Inventors: Gautam GANGULY, Valery KUGEL, Omar AHMED, Leif HUTCHINSON, Peng SU, Matthew TWAROG, Attila I. ARANYOSI, David K. OWEN, Chang-Hong WU, Aliaskar HASSANZADEH, Boris REYNOV, Muhammad SAGARWALA
  • Patent number: 10863628
    Abstract: A printed circuit board (PCB) may include a plurality of horizontally disposed signal layers. The PCB may include a first vertically disposed differential via electrically connected to a first horizontally disposed signal layer, of the plurality of horizontally disposed signal layers, and a second horizontally disposed signal layer of the plurality of horizontally disposed signal layers. The PCB may include a second vertically disposed differential via electrically connected to the first signal horizontally disposed layer and the second horizontally disposed signal layer. The PCB may include a first set of clearances encompassing the first vertically disposed differential via and the second vertically disposed differential via, a second set of clearances encompassing the first vertically disposed stub, and a third set of clearances encompassing the second vertically disposed stub.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: December 8, 2020
    Assignee: Juniper Networks, Inc.
    Inventors: Matthew Twarog, Hui He, Thomas W. Jetton
  • Publication number: 20200053880
    Abstract: A printed circuit board (PCB) may include a plurality of horizontally disposed signal layers. The PCB may include a first vertically disposed differential via electrically connected to a first horizontally disposed signal layer, of the plurality of horizontally disposed signal layers, and a second horizontally disposed signal layer of the plurality of horizontally disposed signal layers. The PCB may include a second vertically disposed differential via electrically connected to the first signal horizontally disposed layer and the second horizontally disposed signal layer. The PCB may include a first set of clearances encompassing the first vertically disposed differential via and the second vertically disposed differential via, a second set of clearances encompassing the first vertically disposed stub, and a third set of clearances encompassing the second vertically disposed stub.
    Type: Application
    Filed: October 17, 2019
    Publication date: February 13, 2020
    Inventors: Matthew TWAROG, Hui HE, Thomas W. JETTON
  • Patent number: 10470311
    Abstract: A printed circuit board (PCB) may include a plurality of horizontally disposed signal layers. The PCB may include a first vertically disposed differential via electrically connected to a first horizontally disposed signal layer, of the plurality of horizontally disposed signal layers, and a second horizontally disposed signal layer of the plurality of horizontally disposed signal layers. The PCB may include a second vertically disposed differential via electrically connected to the first signal horizontally disposed layer and the second horizontally disposed signal layer. The PCB may include a first set of clearances encompassing the first vertically disposed differential via and the second vertically disposed differential via, a second set of clearances encompassing the first vertically disposed stub, and a third set of clearances encompassing the second vertically disposed stub.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: November 5, 2019
    Assignee: Juniper Networks, Inc.
    Inventors: Matthew Twarog, Hui He, Thomas W. Jetton
  • Publication number: 20190098765
    Abstract: A printed circuit board (PCB) may include a plurality of horizontally disposed signal layers. The PCB may include a first vertically disposed differential via electrically connected to a first horizontally disposed signal layer, of the plurality of horizontally disposed signal layers, and a second horizontally disposed signal layer of the plurality of horizontally disposed signal layers. The PCB may include a second vertically disposed differential via electrically connected to the first signal horizontally disposed layer and the second horizontally disposed signal layer. The PCB may include a first set of clearances encompassing the first vertically disposed differential via and the second vertically disposed differential via, a second set of clearances encompassing the first vertically disposed stub, and a third set of clearances encompassing the second vertically disposed stub.
    Type: Application
    Filed: September 28, 2017
    Publication date: March 28, 2019
    Inventors: Matthew TWAROG, Hui He, Thomas W. Jetton