Patents by Inventor Matthew V. Metz
Matthew V. Metz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11978799Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.Type: GrantFiled: January 13, 2021Date of Patent: May 7, 2024Assignee: Tahoe Research, Ltd.Inventors: Justin K. Brask, Robert S. Chau, Suman Datta, Mark L. Doczy, Brian S. Doyle, Jack T. Kavalieros, Amlan Majumdar, Matthew V. Metz, Marko Radosavljevic
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Patent number: 11980037Abstract: Described herein are ferroelectric (FE) memory cells that include transistors having gate stacks separate from FE capacitors of these cells. An example memory cell may be implemented as an IC device that includes a support structure (e.g., a substrate) and a transistor provided over the support structure and including a gate stack. The IC device also includes a FE capacitor having a first capacitor electrode, a second capacitor electrode, and a capacitor insulator of a FE material between the first capacitor electrode and the second capacitor electrode, where the FE capacitor is separate from the gate stack (i.e., is not integrated within the gate stack and does not have any layers that are part of the gate stack). The IC device further includes an interconnect structure, configured to electrically couple the gate stack and the first capacitor electrode.Type: GrantFiled: June 19, 2020Date of Patent: May 7, 2024Assignee: Intel CorporationInventors: Nazila Haratipour, Shriram Shivaraman, Sou-Chi Chang, Jack T. Kavalieros, Uygar E. Avci, Chia-Ching Lin, Seung Hoon Sung, Ashish Verma Penumatcha, Ian A. Young, Devin R. Merrill, Matthew V. Metz, I-Cheng Tung
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Publication number: 20240120415Abstract: Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be etched away, leaving the doped semiconductor layers as fins for a ribbon FET. A ferroelectric layer can be conformally grown on the fins, creating a high-quality ferroelectric layer above and below the fins. A gate can then be grown on the ferroelectric layer.Type: ApplicationFiled: October 1, 2022Publication date: April 11, 2024Applicant: Intel CorporationInventors: Scott B. Clendenning, Sudarat Lee, Kevin P. O'Brien, Rachel A. Steinhardt, John J. Plombon, Arnab Sen Gupta, Charles C. Mokhtarzadeh, Gauri Auluck, Tristan A. Tronic, Brandon Holybee, Matthew V. Metz, Dmitri Evgenievich Nikonov, Ian Alexander Young
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Publication number: 20240113212Abstract: Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers, such as undoped semiconductor layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be preferentially etched away, leaving the doped semiconductor layers as fins for a ribbon FET. In another embodiment, an interlayer can be deposited on top of a semiconductor layer, and a ferroelectric layer can be deposited on the interlayer. The interlayer can bridge a gap in lattice parameters between the semiconductor layer and the ferroelectric layer.Type: ApplicationFiled: September 29, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Ian Alexander Young, Dmitri Evgenievich Nikonov, Marko Radosavljevic, Matthew V. Metz, John J. Plombon, Raseong Kim, Kevin P. O'Brien, Scott B. Clendenning, Tristan A. Tronic, Dominique A. Adams, Carly Rogan, Hai Li, Arnab Sen Gupta, Gauri Auluck, I-Cheng Tung, Brandon Holybee, Rachel A. Steinhardt, Punyashloka Debashis
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Publication number: 20240113161Abstract: A transistor includes a body of semiconductor material, where the body has laterally opposed body sidewalls and a top surface. A gate structure contacts the top surface of the body. A source region contacts a first one of the laterally opposed body sidewalls and a drain region contacts a second one of the laterally opposed body sidewalls. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).Type: ApplicationFiled: December 14, 2023Publication date: April 4, 2024Inventors: Willy RACHMADY, Cheng-Ying HUANG, Matthew V. METZ, Nicholas G. MINUTILLO, Sean T. MA, Anand S. MURTHY, Jack T. KAVALIEROS, Tahir GHANI, Gilbert DEWEY
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Publication number: 20240113220Abstract: Technologies for a transistor with a thin-film ferroelectric gate dielectric are disclosed. In the illustrative embodiment, a transistor has a thin layer of scandium aluminum nitride (ScxAl1-xN) ferroelectric gate dielectric. The channel of the transistor may be, e.g., gallium nitride or molybdenum disulfide. In one embodiment, the ferroelectric polarization changes when voltage is applied and removed from a gate electrode, facilitating switching of the transistor at a lower applied voltage. In another embodiment, the ferroelectric polarization of a gate dielectric of a transistor changes when the voltage is past a positive threshold value or a negative threshold value. Such a transistor can be used as a one-transistor memory cell.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Arnab Sen Gupta, Ian Alexander Young, Dmitri Evgenievich Nikonov, Marko Radosavljevic, Matthew V. Metz, John J. Plombon, Raseong Kim, Uygar E. Avci, Kevin P. O'Brien, Scott B. Clendenning, Jason C. Retasket, Shriram Shivaraman, Dominique A. Adams, Carly Rogan, Punyashloka Debashis, Brandon Holybee, Rachel A. Steinhardt, Sudarat Lee
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Publication number: 20240105810Abstract: In one embodiment, transistor device includes a first source or drain material on a substrate, a semiconductor material on the first source or drain material, a second source or drain material on the semiconductor material, a dielectric layer on the substrate and adjacent the first source or drain material, a ferroelectric (FE) material on the dielectric layer and adjacent the semiconductor material, and a gate material on or adjacent to the FE material. The FE material may be a perovskite material and may have a lattice parameter that is less than a lattice parameter of the semiconductor material.Type: ApplicationFiled: September 23, 2022Publication date: March 28, 2024Applicant: Intel CorporationInventors: Rachel A. Steinhardt, Ian Alexander Young, Dmitri Evgenievich Nikonov, Marko Radosavljevic, Matthew V. Metz, John J. Plombon, Raseong Kim, Kevin P. O'Brien, Scott B. Clendenning, Tristan A. Tronic, Dominique A. Adams, Carly Rogan, Arnab Sen Gupta, Brandon Holybee, Punyashloka Debashis, I-Cheng Tung, Gauri Auluck
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Publication number: 20240105588Abstract: An IC device includes a multilayer metal line that is at least partially surrounded by one or more electrical insulators. The multilayer metal line may be formed by stacking four layers on top of one another. The four layers may include a first layer between a second layer and a third layer. The first layer may include Al. The second or third layer may include W. The fourth layer may be a conductive or dielectric layer. The second layer, third layer, and fourth layer can protect the first layer from defects in Al core layer during fabrication or operation of the multilayer metal line. Substrative etch may be performed on the stack of the four layers to form openings. An electrical insulator may be deposited into to the openings to form multiple metal lines that are separated by the electrical insulator. A via may be formed over the third layer.Type: ApplicationFiled: September 28, 2022Publication date: March 28, 2024Applicant: Intel CorporationInventors: Ilya V. Karpov, Shafaat Ahmed, Matthew V. Metz, Darren Anthony Denardis, Nafees Aminul Kabir, Tristan A. Tronic
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Publication number: 20240097031Abstract: In one embodiment, a transistor device includes a gate material layer on a substrate, a ferroelectric (FE) material layer on the gate material, a semiconductor channel material layer on the FE material layer, a first source/drain material on the FE material layer and adjacent the semiconductor channel material layer, and a second source/drain material on the FE material layer and adjacent the semiconductor channel material layer and on an opposite side of the semiconductor channel material layer from the first source/drain material. A first portion of the FE material layer is directly between the gate material and the first source/drain material, and a second portion of the FE material layer is directly between the gate material and the second source/drain material.Type: ApplicationFiled: September 16, 2022Publication date: March 21, 2024Applicant: Intel CorporationInventors: Punyashloka Debashis, Rachel A. Steinhardt, Brandon Holybee, Kevin P. O'Brien, Dmitri Evgenievich Nikonov, John J. Plombon, Ian Alexander Young, Raseong Kim, Carly Rogan, Dominique A. Adams, Arnab Sen Gupta, Marko Radosavljevic, Scott B. Clendenning, Gauri Auluck, Hai Li, Matthew V. Metz, Tristan A. Tronic, I-Cheng Tung
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Publication number: 20240088143Abstract: Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.Type: ApplicationFiled: November 21, 2023Publication date: March 14, 2024Inventors: Szuya S. Liao, Scott B. CLENDENNING, Jessica TORRES, Lukas BAUMGARTEL, Kiran CHIKKADI, Diane LANCASTER, Matthew V. METZ, Florian GSTREIN, Martin M. MITAN, Rami HOURANI
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Patent number: 11929435Abstract: Techniques are disclosed for an integrated circuit including a ferroelectric gate stack including a ferroelectric layer, an interfacial oxide layer, and a gate electrode. The ferroelectric layer can be voltage activated to switch between two ferroelectric states. Employing such a ferroelectric layer provides a reduction in leakage current in an off-state and provides an increase in charge in an on-state. The interfacial oxide layer can be formed between the ferroelectric layer and the gate electrode. Alternatively, the ferroelectric layer can be formed between the interfacial oxide layer and the gate electrode.Type: GrantFiled: August 30, 2022Date of Patent: March 12, 2024Assignee: Intel CorporationInventors: Gilbert Dewey, Willy Rachmady, Jack T. Kavalieros, Cheng-Ying Huang, Matthew V. Metz, Sean T. Ma, Harold Kennel, Tahir Ghani
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Patent number: 11923290Abstract: Embodiments disclosed herein include semiconductor devices with source/drain interconnects that include a barrier layer. In an embodiment the semiconductor device comprises a source region and a drain region. In an embodiment, a semiconductor channel is between the source region and the drain region, and a gate electrode is over the semiconductor channel. In an embodiment, the semiconductor device further comprises interconnects to the source region and the drain region. In an embodiment, the interconnects comprise a barrier layer, a metal layer, and a fill metal.Type: GrantFiled: June 26, 2020Date of Patent: March 5, 2024Assignee: Intel CorporationInventors: Siddharth Chouksey, Gilbert Dewey, Nazila Haratipour, Mengcheng Lu, Jitendra Kumar Jha, Jack T. Kavalieros, Matthew V. Metz, Scott B Clendenning, Eric Charles Mattson
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Patent number: 11923410Abstract: A transistor includes a body of semiconductor material, where the body has laterally opposed body sidewalls and a top surface. A gate structure contacts the top surface of the body. A source region contacts a first one of the laterally opposed body sidewalls and a drain region contacts a second one of the laterally opposed body sidewalls. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).Type: GrantFiled: October 4, 2021Date of Patent: March 5, 2024Assignee: Intel CorporationInventors: Willy Rachmady, Cheng-Ying Huang, Matthew V. Metz, Nicholas G. Minutillo, Sean T. Ma, Anand S. Murthy, Jack T. Kavalieros, Tahir Ghani, Gilbert Dewey
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Patent number: 11869889Abstract: Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.Type: GrantFiled: September 23, 2019Date of Patent: January 9, 2024Assignee: Intel CorporationInventors: Szuya S. Liao, Scott B. Clendenning, Jessica Torres, Lukas Baumgartel, Kiran Chikkadi, Diane Lancaster, Matthew V. Metz, Florian Gstrein, Martin M. Mitan, Rami Hourani
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Publication number: 20240006494Abstract: Semiconductor structures having a source and/or drain with a refractory metal cap, and methods of forming the same, are described herein. In one example, a semiconductor structure includes a channel, a gate, a source, and a drain. The source and drain contain silicon and germanium, and one or both of the source and drain are capped with a semiconductor cap and a refractory metal cap. The semiconductor cap is on the source and/or drain and contains germanium and boron. The refractory metal cap is on the semiconductor cap and contains a refractory metal.Type: ApplicationFiled: July 1, 2022Publication date: January 4, 2024Applicant: Intel CorporationInventors: Nazila Haratipour, Gilbert Dewey, Nancy Zelick, Siddharth Chouksey, I-Cheng Tung, Arnab Sen Gupta, Jitendra Kumar Jha, Chi-Hing Choi, Matthew V. Metz, Jack T. Kavalieros
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Publication number: 20240006484Abstract: Embodiments disclosed herein include transistors and methods of forming transistors. In an embodiment, the transistor comprises a channel with a first end and a second end opposite from the first end, a first spacer around the first end of the channel, a second spacer around the second end of the channel, and a gate stack over the channel, where the gate stack is between the first spacer and the second spacer. In an embodiment, the transistor may further comprise a first extension contacting the first end of the channel; and a second extension contacting the first end of the channel. In an embodiment, the transistor further comprises conductive layers over the first extension and the second extension outside of the first spacer and the second spacer.Type: ApplicationFiled: June 30, 2022Publication date: January 4, 2024Inventors: Ashish Verma PENUMATCHA, Kevin P. O'BRIEN, Kirby MAXEY, Carl H. NAYLOR, Chelsey DOROW, Uygar E. AVCI, Matthew V. METZ, Sudarat LEE, Chia-Ching LIN, Sean T. MA
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Publication number: 20240006533Abstract: Contacts to p-type source/drain regions comprise a boride, indium, or gallium metal compound layer. The boride, indium, or gallium metal compound layers can aid in forming thermally stable low resistance contacts. A boride, indium, or gallium metal compound layer is positioned between the source/drain region and the contact metal layer. A boride, indium, or gallium metal compound layer can be used in contacts contacting p-type source/drain regions comprising boron, indium, or gallium as the primary dopant, respectively. The boride, indium, or gallium metal compound layers prevent diffusion of boron, indium, or gallium from the source/drain region into the metal contact layer and dopant deactivation in the source/drain region due to annealing and other high-temperature processing steps that occur after contact formation.Type: ApplicationFiled: July 2, 2022Publication date: January 4, 2024Applicant: Intel CorporationInventors: Gilbert Dewey, Siddharth Chouksey, Nazila Haratipour, Christopher Jezewski, Jitendra Kumar Jha, Ilya V. Karpov, Matthew V. Metz, Arnab Sen Gupta, I-Cheng Tung, Nancy Zelick, Chi-Hing Choi, Dan S. Lavric
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Publication number: 20240006488Abstract: In one embodiment, layers comprising Carbon (e.g., Silicon Carbide) are on source/drain regions of a transistor, e.g., before gate formation and metallization, and the layers comprising Carbon are later removed in the manufacturing process to form electrical contacts on the source/drain regions.Type: ApplicationFiled: July 1, 2022Publication date: January 4, 2024Applicant: Intel CorporationInventors: Nazila Haratipour, Gilbert Dewey, Nancy Zelick, Siddharth Chouksey, I-Cheng Tung, Arnab Sen Gupta, Jitendra Kumar Jha, David Kohen, Natalie Briggs, Chi-Hing Choi, Matthew V. Metz, Jack T. Kavalieros
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Publication number: 20230420511Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for a transistor structure that includes stacked nanoribbons as a single crystal or monolayer, such as a transition metal dichalcogenide (TMD) layer, grown on a silicon wafer using a seeding material. Other embodiments may be described and/or claimed.Type: ApplicationFiled: June 27, 2022Publication date: December 28, 2023Inventors: Carl H. NAYLOR, Kirby MAXEY, Kevin P. O'BRIEN, Chelsey DOROW, Sudarat LEE, Ashish Verma PENUMATCHA, Uygar E. AVCI, Matthew V. METZ, Scott B. CLENDENNING, Chia-Ching LIN, Carly ROGAN, Arnab SEN GUPTA
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Publication number: 20230420246Abstract: An integrated circuit structure includes a source or drain region, and a contact coupled to the source or drain region. A region including metals and semiconductor materials is between the source or drain region and the contact. A first dopant is within the source or drain region, and a second dopants is within the region. In one example, the first dopant is elementally different from the second dopant. In another example, the first dopant is elementally same as the second dopant, wherein a concentration of the first dopant within a section of the source or drain region is within 20% of a concentration of the second dopant within the region, and wherein the section of the source or drain region is at a distance of at most 5 nanometers (nm) from the region.Type: ApplicationFiled: June 23, 2022Publication date: December 28, 2023Applicant: Intel CorporationInventors: Ilya V. Karpov, Aaron A. Budrevich, Gilbert Dewey, Matthew V. Metz, Jack T. Kavalieros, Dan S. Lavric