Patents by Inventor Matthew van Adelsberg

Matthew van Adelsberg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11385901
    Abstract: A system including: at least one processor; and at least one memory having stored thereon computer program code that, when executed by the at least one processor, controls the system to: receive a data model identification and a dataset; in response to determining that the data model does not contain a hierarchical structure, perform expectation propagation on the dataset to approximate the data model with a hierarchical structure; divide the dataset into a plurality of channels; for each of the plurality of channels: divide the data into a plurality of microbatches; process each microbatch of the plurality of microbatches through parallel iterators; and process the output of the parallel iterators through single-instruction multiple-data (SIMD) layers; and asynchronously merge results of the SIMD layers.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: July 12, 2022
    Assignee: CAPITAL ONE SERVICES, LLC
    Inventors: Matthew van Adelsberg, Rohit Joshi, Siqi Wang
  • Publication number: 20200348941
    Abstract: A system including: at least one processor; and at least one memory having stored thereon computer program code that, when executed by the at least one processor, controls the system to: receive a data model identification and a dataset; in response to determining that the data model does not contain a hierarchical structure, perform expectation propagation on the dataset to approximate the data model with a hierarchical structure; divide the dataset into a plurality of channels; for each of the plurality of channels: divide the data into a plurality of microbatches; process each microbatch of the plurality of microbatches through parallel iterators; and process the output of the parallel iterators through single-instruction multiple-data (SIMD) layers; and asynchronously merge results of the SIMD layers.
    Type: Application
    Filed: May 13, 2020
    Publication date: November 5, 2020
    Inventors: Matthew van Adelsberg, Rohit Joshi, Siqi Wang
  • Patent number: 10732983
    Abstract: A system including: at least one processor; and at least one memory having stored thereon computer program code that, when executed by the at least one processor, controls the system to: receive a data model identification and a dataset; in response to determining that the data model does not contain a hierarchical structure, perform expectation propagation on the dataset to approximate the data model with a hierarchical structure; divide the dataset into a plurality of channels; for each of the plurality of channels: divide the data into a plurality of microbatches; process each microbatch of the plurality of microbatches through parallel iterators; and process the output of the parallel iterators through single-instruction multiple-data (SIMD) layers; and asynchronously merge results of the SIMD layers.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: August 4, 2020
    Assignee: CAPITAL ONE SERVICES, LLC
    Inventors: Matthew van Adelsberg, Rohit Joshi, Siqi Wang