Abstract: A data processing system for implementing operations that generate a dynamically-sized output is presented. The data processing system includes a reconfigurable processor that is configured to implement a first operation, a second operation, a recording unit, and a control unit. The first operation generates an output, wherein a size of the output is unknown during a configuration phase. The second operation receives the output of the first operation as an input. The recording unit generates control data that is indicative of the size of the output. The control unit that provides the control data to the second operation, wherein the second operation processes the input based on the control data.

Abstract: A data processing system for implementing operations that generate a dynamically-sized output comprises a reconfigurable processor and a compiler. The compiler generates configuration data for configuring the reconfigurable processor to implement first and second operations and first and second connections. The first operation generates an output, and the second operation receives the output of the first operation as an input. The size of the output is unknown when generating the configuration data, and the output comprises a number of elements that is smaller than or equal to a predetermined maximum number of elements. The first connection for the output and the second connection for the input are both suitable for a transmission of the predetermined maximum number of elements. The reconfigurable processor is configured with the configuration data such that the reconfigurable processor implements the first operation, the second operation, the first connection, and the second connection.

Abstract: A data processing system for implementing operations that generate a dynamically-sized output includes a reconfigurable processor that is configured to implement first and second operations and control circuitry. The first operation generates an output, whose size is unknown during a configuration phase. The second operation receives the output as an input. During a write operation, the first operation is enabled to write a first portion of the output to a first portion of a buffer, while the second operation reads a first portion of the input that is different than the first portion of the output from a second portion of the buffer that is different than the first portion of the buffer. The control circuity includes a control unit that: directs the second operation during a read operation following the write operation to read data as the input from the buffer that was stored during the write operation.

Abstract: In some aspects, a program is executed on a coarse-grained reconfigurable (CGR) processor. The CGR determines that the program produces an output that includes a variable length tensor, determines a maximum size of the variable length tensor and sets, based on the maximum size, a maximum of a counter associated with the program. The counter is set to an initial value of zero. The CGR initiates execution of the program, causing the program to receive an input tensor. Based on determining that the program is operating on a first portion of the input tensor, the CGR performs an update to the counter, to create an updated counter, and communicates the updated counter to one or more consumers within the program. After determining that the program has completed operating on the input tensor, a final size of the output is communicated to one or more downstream consumers external to the program.

Abstract: A statically reconfigurable dataflow architecture processor (SRDAP) performs an N-dimensional affine transform specified by a matrix on an input image to produce an output image includes pattern compute units (PCUs) and pattern memory units (PMUs) interconnected by switches. PCUs have vector pipelines of functional units that perform operations on operands received from previous pipeline stages, another PCU, and/or PMUs. PMUs have memories loadable with the input image. The PCUs and PMUs are statically reconfigurable to, for all the output pixels: apply the matrix to vectors of output pixel coordinates to calculate corresponding vectors of input pixel coordinates, flatten the vectors of input pixel coordinates into vectors of PMU addresses of the input pixels, read values of the input pixels from the PMUs at the calculated input pixel addresses, and write vectors of the input pixel values to PMUs to form the output image.

Abstract: A statically reconfigurable dataflow architecture processor performs an N-dimensional affine transform specified by a matrix on an input image to produce an output image includes at least N+1 statically reconfigurable pattern compute units (PCUs) and pattern memory units (PMUs) each comprising a memory arranged as a vector of L banks. A first PMU writes a copy of the input image into each of the L banks. Each of N of the PCUs associated with the N dimensions is statically reconfigurable to apply a respective row of the transform matrix to N L-vectors of output pixel coordinates to generate a respective L-vector of input pixel coordinates. At least one of the PCUs flattens the N L-vectors of input pixel coordinates to calculate an L-vector of addresses. The first PMU uses the L addresses of the L-vector of addresses to read an L-vector of input pixels from the L banks in parallel.

Abstract: A statically reconfigurable dataflow architecture processor performs an N-dimensional affine transform specified by a matrix on an input image to produce an output image. N counters iterate over the output image by N respective stride values (N output tile dimension lengths) to generate base pixel coordinates of N-dimensional output tiles into which the output image is subdividable. Statically reconfigurable pattern compute units, for each output tile of the output tiles: use the base pixel coordinates of the output tile and the N output tile dimension lengths to calculate the coordinates of corner pixels of the output tile and apply the affine transform matrix to the corner pixel coordinates and use the results to determine base pixel coordinates of a corresponding N-dimensional input tile into which the input image is subdividable. Statically reconfigurable pattern memory units load each corresponding input tile based on the determined input tile base pixel coordinates.

Abstract: A statically reconfigurable dataflow architecture processor (SRDAP) performs an N-dimensional affine transform specified by a matrix on an input image to produce an output image includes L address pattern memory units (PMUs) comprising a memory arranged as a vector of L banks, and L corresponding data PMUs. Each data PMU receives a copy of the input image. In parallel: each address PMU writes an L-vector of addresses of input pixels to the vector of L banks and reads a single address of the written L-vector of addresses from a predetermined bank corresponding to a PMU number of the address PMU among the L address PMUs, and each data PMU receives the single address from the corresponding address PMU and uses it to read a single input pixel from the data PMU memory. A tree of pattern compute units coalesces the L single input pixels into an L-vector of input pixels.

Abstract: A data processing system for implementing operations that generate a dynamically-sized output is presented. The data processing system includes a reconfigurable processor that is configured to implement a first operation, a second operation, a recording unit, and a control unit. The first operation generates an output, wherein a size of the output is unknown during a configuration phase. The second operation receives the output of the first operation as an input. The recording unit generates control data that is indicative of the size of the output. The control unit that provides the control data to the second operation, wherein the second operation processes the input based on the control data.