Abstract: Conventional high performance computer connections are electron-based systems, which require the memory packages to be as close as mechanically possible to the computation engine. Low power and high bandwidth communication, e.g. photonic, links can drastically change the architecture of high-performance computers by eliminating the bottlenecks in communication and augment existing memory systems to allow them to be both high capacity and high bandwidth simultaneously.

Abstract: Methods and systems for navigating to a target through a patient's bronchial tree are disclosed including a bronchoscope, a probe insertable into a working channel of the bronchoscope and including a location sensor, and a workstation in operative communication with the probe and the bronchoscope, the workstation including a user interface that guides a user through a navigation plan and is configured to present a central navigation view including a plurality of views configured for assisting the user in navigating the bronchoscope through central airways of the patient's bronchial tree toward the target, a peripheral navigation view including a plurality of views configured for assisting the user in navigating the probe through peripheral airways of the patient's bronchial tree to the target, and a target alignment view including a plurality of views configured for assisting the user in aligning a distal tip of the probe with the target.

Abstract: Methods and systems for navigating to a target through a patient's bronchial tree are disclosed including a bronchoscope, a probe insertable into a working channel of the bronchoscope and including a location sensor, and a workstation in operative communication with the probe and the bronchoscope, the workstation including a user interface that guides a user through a navigation plan and is configured to present a central navigation view including a plurality of views configured for assisting the user in navigating the bronchoscope through central airways of the patient's bronchial tree toward the target, a peripheral navigation view including a plurality of views configured for assisting the user in navigating the probe through peripheral airways of the patient's bronchial tree to the target, and a target alignment view including a plurality of views configured for assisting the user in aligning a distal tip of the probe with the target.

Abstract: Methods and systems for navigating to a target through a patient's bronchial tree are disclosed including a bronchoscope, a probe insertable into a working channel of the bronchoscope and including a location sensor, and a workstation in operative communication with the probe and the bronchoscope, the workstation including a user interface that guides a user through a navigation plan and is configured to present a central navigation view including a plurality of views configured for assisting the user in navigating the bronchoscope through central airways of the patient's bronchial tree toward the target, a peripheral navigation view including a plurality of views configured for assisting the user in navigating the probe through peripheral airways of the patient's bronchial tree to the target, and a target alignment view including a plurality of views configured for assisting the user in aligning a distal tip of the probe with the target.

Abstract: Methods and systems for navigating to a target through a patient's bronchial tree are disclosed including a bronchoscope, a probe insertable into a working channel of the bronchoscope and including a location sensor, and a workstation in operative communication with the probe and the bronchoscope, the workstation including a user interface that guides a user through a navigation plan and is configured to present a central navigation view including a plurality of views configured for assisting the user in navigating the bronchoscope through central airways of the patient's bronchial tree toward the target, a peripheral navigation view including a plurality of views configured for assisting the user in navigating the probe through peripheral airways of the patient's bronchial tree to the target, and a target alignment view including a plurality of views configured for assisting the user in aligning a distal tip of the probe with the target.

Abstract: Methods and systems for navigating to a target through a patient's bronchial tree are disclosed including a bronchoscope, a probe insertable into a working channel of the bronchoscope and including a location sensor, and a workstation in operative communication with the probe and the bronchoscope, the workstation including a user interface that guides a user through a navigation plan and is configured to present a central navigation view including a plurality of views configured for assisting the user in navigating the bronchoscope through central airways of the patient's bronchial tree toward the target, a peripheral navigation view including a plurality of views configured for assisting the user in navigating the probe through peripheral airways of the patient's bronchial tree to the target, and a target alignment view including a plurality of views configured for assisting the user in aligning a distal tip of the probe with the target.

Abstract: Methods and systems for navigating to a target through a patient's bronchial tree are disclosed including a bronchoscope, a probe insertable into a working channel of the bronchoscope and including a location sensor, and a workstation in operative communication with the probe and the bronchoscope, the workstation including a user interface that guides a user through a navigation plan and is configured to present a central navigation view including a plurality of views configured for assisting the user in navigating the bronchoscope through central airways of the patient's bronchial tree toward the target, a peripheral navigation view including a plurality of views configured for assisting the user in navigating the probe through peripheral airways of the patient's bronchial tree to the target, and a target alignment view including a plurality of views configured for assisting the user in aligning a distal tip of the probe with the target.

Abstract: Embodiments that design integrated circuits using a 1×N compiler in a closed-loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1×N building blocks. The embodiments may alter elements of the 1×N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a first generator to generate a behavioral representation of a design for an integrated circuit, a second generator to generate a logical representation of the design, and a third generator to generate a physical design representation of the design, wherein the representation generators may create updated versions of the representations which reflect alterations made to 1×N building block elements.

Abstract: Methods and systems for navigating to a target through a patient's bronchial tree are disclosed including a bronchoscope, a probe insertable into a working channel of the bronchoscope and including a location sensor, and a workstation in operative communication with the probe and the bronchoscope, the workstation including a user interface that guides a user through a navigation plan and is configured to present a central navigation view including a plurality of views configured for assisting the user in navigating the bronchoscope through central airways of the patient's bronchial tree toward the target, a peripheral navigation view including a plurality of views configured for assisting the user in navigating the probe through peripheral airways of the patient's bronchial tree to the target, and a target alignment view including a plurality of views configured for assisting the user in aligning a distal tip of the probe with the target.

Abstract: Embodiments that design integrated circuits using a 1×N compiler in a closed-loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1×N building blocks. The embodiments may alter elements of the 1×N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a first generator to generate a behavioral representation of a design for an integrated circuit, a second generator to generate a logical representation of the design, and a third generator to generate a physical design representation of the design, wherein the representation generators may create updated versions of the representations which reflect alterations made to 1×N building block elements.

Abstract: Embodiments that design integrated circuits using a 1×N compiler in a closed-loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1×N building blocks. The embodiments may alter elements of the 1×N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a first generator to generate a behavioral representation of a design for an integrated circuit, a second generator to generate a logical representation of the design, and a third generator to generate a physical design representation of the design, wherein the representation generators may create updated versions of the representations which reflect alterations made to 1×N building block elements.

Abstract: Embodiments that design integrated circuits using a 1×N compiler in a closed-loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1×N building blocks. The embodiments may alter elements of the 1×N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a first generator to generate a behavioral representation of a design for an integrated circuit, a second generator to generate a logical representation of the design, and a third generator to generate a physical design representation of the design, wherein the representation generators may create updated versions of the representations which reflect alterations made to 1×N building block elements.

Abstract: Embodiments that design integrated circuits using a 1×N compiler in a closed-loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1×N building blocks. The embodiments may alter elements of the 1×N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a first generator to generate a behavioral representation of a design for an integrated circuit, a second generator to generate a logical representation of the design, and a third generator to generate a physical design representation of the design, wherein the representation generators may create updated versions of the representations which reflect alterations made to 1×N building block elements.

Abstract: Embodiments that design integrated circuits using a 1×N compiler in a closed-loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1×N building blocks. The embodiments may alter elements of the 1×N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a first generator to generate a behavioral representation of a design for an integrated circuit, a second generator to generate a logical representation of the design, and a third generator to generate a physical design representation of the design, wherein the representation generators may create updated versions of the representations which reflect alterations made to 1×N building block elements.

Abstract: Embodiments that create parent-child relationships for reuse of 1×N building blocks in a closed-loop 1×N system are disclosed. Some methods comprise generating a representation of an IC design, inserting a first 1×N building block into the representation, and creating an association between the first 1×N building block and a second 1×N building block. The association enables the first 1×N building block to inherit alterations of attributes of the second 1×N building block and enables unique alterations of attributes of the first 1×N building block which differ from the second 1×N building block. Further embodiments comprise an apparatus having an equivalency determiner to determine a logical equivalence between a two 1×N building blocks, an attribute creator that creates a set of attributes and enables one of the 1×N building blocks to inherit parent attributes and comprise child attributes.

Abstract: Embodiments that make DFM alterations to cells of 1×N building blocks via a closed-loop 1×N compiler are disclosed. Some embodiments comprise using a 1×N compiler to detect a relationship between two adjacent cells of a 1×N building block. Based on the relationship, the embodiments select a DFM alteration and apply the alteration to a physical design representation. The embodiments may apply various types of DFM alterations depending on the relationship, such as adding polysilicon, adding metal to create redundant connections, and merging diffusion areas to increase capacitance on supply nodes. Further embodiments comprise an apparatus having a cell examiner to examine two adjacent cells of a 1×N building block and determine a relationship of the two cells. The apparatus also comprises a DFM selector to select a DFM alteration based on the relationship and a DFM applicator to apply the selected DFM alteration to one of the cells.

Abstract: Embodiments that reassemble hierarchical representations in a closed-loop 1×N system are disclosed. Some embodiments comprise creating a flat netlist from a hierarchical representation of a 1×N building block, creating attributes for the flat netlist, and altering one or more elements of the flat netlist, such as by an operation of a logic design tool, a synthesis tool, a physical design tool, or a timing analysis tool. The embodiments further comprise generating a second hierarchical representation of the 1×N building block that reflects the altered element. Further embodiments comprise an apparatus having a 1×N compiler and a reassembler. The 1×N compiler may create attributes for a flat netlist of elements of a hierarchical representation of a 1×N building block. The reassembler may use the attributes to create a second hierarchical representation of the 1×N building block that reflects alteration of elements to the flat netlist.

Abstract: Embodiments that design integrated circuits using a closed loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1×N building blocks. The embodiments may alter elements of the 1×N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a viewer and a 1×N compiler. The viewer may generate displays of behavioral representations of 1×N building blocks, with the behavioral representations comprising RTL definitions. The 1×N compiler may create physical design representations of the 1×N building block and create behavioral representations from the physical design representations, wherein the physical design representations have elements altered by one or more tools of a tool suite.

Abstract: Embodiments that design integrated circuits using a 1×N compiler in a closed-loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1×N building blocks. The embodiments may alter elements of the 1×N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a first generator to generate a behavioral representation of a design for an integrated circuit, a second generator to generate a logical representation of the design, and a third generator to generate a physical design representation of the design, wherein the representation generators may create updated versions of the representations which reflect alterations made to 1×N building block elements.

Abstract: An apparatus, method and product for selecting an iSCSI target for us in automatically booting a remote initiator is disclosed. A policy engine is created for use in a discovery domain of an iSCSI device. A boot attribute setting within the policy engine is set for selecting an iSCSI target to allow the remote initiator to automatically log onto the selected target for booting.