Abstract: Methods and apparatus to provide ultra low voltage, low leakage, high density, and/or variation tolerant memory bit cells are described. In one embodiment, each of the cross-coupled invertors of a memory cell may include a plurality of p-channel transistors. Other embodiments are also described.

Abstract: Methods and apparatus to provide ultra low voltage, low leakage, high density, and/or variation tolerant memory bit cells are described. In one embodiment, each of the cross-coupled invertors of a memory cell may include a plurality of p-channel transistors. Other embodiments are also described.

Abstract: A multiplexer is provided that is symmetric in that substantially the same delay is experienced from any input of the multiplexer to the multiplexer output. It is realized that in conventional serial transmission systems, standard Current Mode Logic (CML) multiplexers are used which are asymmetric and exhibit different delays between select and data inputs. Because of these delays, conventional transmission systems experience jitter at high frequencies. To extend the operable range of communication systems, a symmetric multiplexer may be used which has substantially the same delay from any input to the multiplexed output, thus reducing jitter. For example, the multiplexer may be part of a communication system having a serial data transmission circuit.