Patents by Inventor Matthew W. Heath

Matthew W. Heath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8553503
    Abstract: In one embodiment, a timing relationship between two signals on an integrated circuit is measured using a ring oscillator on the die of the integrated circuit. The measured time difference is outputted in a digital form. A delay line coupled to the ring oscillator may be used to reduce uncertainty in measurement which may result from the effects of latch circuit metastability. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: October 8, 2013
    Assignee: Intel Corporation
    Inventors: Igor V. Molchanov, Matthew W. Heath
  • Publication number: 20100306437
    Abstract: A method and apparatus to selectively extend an embedded microprocessor bus through a different external bus are generally presented. In this regard, an apparatus is introduced comprising a first high speed serializer/deserializer (SERDES) bus internal to an integrated circuit device to couple an embedded microprocessor with an embedded component, a second high speed SERDES bus different from the first bus to couple the embedded component with an external interface of the integrated circuit device, and extension circuitry to selectively bypass the embedded component and extend the first bus to function at the external interface over a physical layer of the second bus. Other embodiments are also described and claimed.
    Type: Application
    Filed: May 26, 2009
    Publication date: December 2, 2010
    Inventors: Matthew W. Heath, Mohan K. Nair, Guadalupe J. Garcia, Bibbin Chacko, Timothy F. Waite, Mark A. Yarch, Hang T. Nguyen, Saiyid Al-Mahmood, Lyonel Renaud, Ganesh Kondapuram, Richard L. Stout
  • Publication number: 20100164476
    Abstract: In one embodiment, a timing relationship between two signals on an integrated circuit is measured using a ring oscillator on the die of the integrated circuit. The measured time difference is outputted in a digital form. A delay line coupled to the ring oscillator may be used to reduce uncertainty in measurement which may result from the effects of latch circuit metastability. Other embodiments are described and claimed.
    Type: Application
    Filed: December 31, 2008
    Publication date: July 1, 2010
    Inventors: Igor V. MOLCHANOV, Matthew W. HEATH
  • Patent number: 7587650
    Abstract: A detector to detect the magnitude of the jitter that may occur in a first clock signal and a second clock signal and to generate an alarm signal if the magnitude of the jitter exceeds the threshold value. The detector comprises a one-hot register storing a one-hot value comprising a first logic bit (=1) centered around one or more second logic bits (=0). The detector comprises a threshold register storing a threshold value comprising one or more second logic bits centered around one or more first logic bits. An event of a first clock rotates the contents of the one-hot value and an event of a second clock rotates the contents of the threshold value. A match between the pre-specified bit of the one-hot value and the threshold value indicates the occurrence of the jitter having a magnitude greater than the threshold value.
    Type: Grant
    Filed: December 8, 2006
    Date of Patent: September 8, 2009
    Assignee: Intel Corporation
    Inventors: Matthew W. Heath, Mark Waggoner, Robert Greiner, Brett W. Newkirk
  • Publication number: 20080141101
    Abstract: A detector to detect the magnitude of the jitter that may occur in a first clock signal and a second clock signal and to generate an alarm signal if the magnitude of the jitter exceeds the threshold value. The detector comprises a one-hot register storing a one-hot value comprising a first logic bit (=1) centered around one or more second logic bits (=0). The detector comprises a threshold register storing a threshold value comprising one or more second logic bits centered around one or more first logic bits. An event of a first clock rotates the contents of the one-hot value and an event of a second clock rotates the contents of the threshold value. A match between the pre-specified bit of the one-hot value and the threshold value indicates the occurrence of the jitter having a magnitude greater than the threshold value.
    Type: Application
    Filed: December 8, 2006
    Publication date: June 12, 2008
    Inventors: Matthew W. Heath, Mark Waggoner, Robert Greiner, Brett W. Newkirk