Patents by Inventor Matthew W. Stoker
Matthew W. Stoker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230146952Abstract: The present disclosure relates to semiconductor structures and, more particularly, to transistors with faceted raised source/drain regions and methods of manufacture. The structure includes: a substrate; a gate structure on the substrate; and faceted, raised source/drain regions adjacent to the gate structure and including at least two different semiconductor materials.Type: ApplicationFiled: November 8, 2021Publication date: May 11, 2023Inventors: George R. MULFINGER, Matthew W. STOKER, Ryan W. SPORER, Man GU
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Patent number: 10529831Abstract: At least one method, apparatus and system providing semiconductor devices comprising a semiconductor substrate; a first fin and a second fin on the semiconductor substrate; a first epitaxial formation on the first fin and having an inner surface oriented toward the second fin and an outer surface oriented away from the second fin; a second epitaxial formation on the second fin and having an inner surface oriented toward the first fin and an outer surface oriented away from the first fin; and a conformal dielectric layer on at least portions of the inner and outer surfaces of the first epitaxial formation, on at least portions of the inner and outer surfaces of the first epitaxial formation and the second epitaxial formation, and merged between the inner surface of the first epitaxial formation and inner surface of the second epitaxial formation.Type: GrantFiled: August 3, 2018Date of Patent: January 7, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Qun Gao, Matthew W. Stoker, Haigou Huang
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Patent number: 10396078Abstract: The disclosure is directed to an integrated circuit structure. The integrated circuit structure may include: a first device region laterally adjacent to a second device region over a substrate, the first device region including a first fin and the second device region including a second fin; a first source/drain epitaxial region substantially surrounding at least a portion of the first fin; a spacer substantially surrounding the first source/drain epitaxial region, the spacer including an opening in a lateral end portion of the spacer such that the lateral end portion of the spacer overhangs a lateral end portion of the first source/drain epitaxial region; and a liner conformally coating the lateral end portion of the first source/drain epitaxial region beneath the overhanging lateral end portion of the spacer, wherein the liner includes an electrical insulator.Type: GrantFiled: June 7, 2018Date of Patent: August 27, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Judson R. Holt, Christopher D. Sheraw, Timothy J. McArdle, Matthew W. Stoker, Mira Park, George R. Mulfinger, Yinxiao Yang
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Patent number: 10204984Abstract: At least one method, apparatus and system disclosed herein involves forming increased surface regions within EPI structures. A fin on a semiconductor substrate is formed. On a top portion of the fin, an epitaxial (EPI) structure is formed. The EPI structure has a first EPI portion having a first material and a second EPI portion having a second material. The first and second EPI portions are separated by a first separation layer. A first cavity is formed within the EPI structure by removing a portion of the second material in the second portion. A first conductive material is deposited into the first cavity.Type: GrantFiled: August 2, 2017Date of Patent: February 12, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Matthew W. Stoker, Judson R. Holt, Timothy J. McArdle, Annie Lévesque
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Publication number: 20190043944Abstract: At least one method, apparatus and system disclosed herein involves forming increased surface regions within EPI structures. A fin on a semiconductor substrate is formed. On a top portion of the fin, an epitaxial (EPI) structure is formed. The EPI structure has a first EPI portion having a first material and a second EPI portion having a second material. The first and second EPI portions are separated by a first separation layer. A first cavity is formed within the EPI structure by removing a portion of the second material in the second portion. A first conductive material is deposited into the first cavity.Type: ApplicationFiled: August 2, 2017Publication date: February 7, 2019Applicant: GLOBALFOUNDRIES INC.Inventors: Matthew W. Stoker, Judson R. Holt, Timothy J. McArdle, Annie Lévesque
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Patent number: 10121706Abstract: One aspect of the disclosure is directed to a method of forming a semiconductor structure. The method including: removing each fin in a set of fins from between insulator pillars to expose a portion of a substrate between each insulator pillar, the substrate having a first device region and a second device region; forming a first material over the exposed portions of the substrate between each insulator pillar, the first material including a two-dimensional material; forming a second material over the first material in the first device region, the second material including a first three-dimensional bonding material; and forming a third material over the exposed first material in the second device region, the third material including a second three-dimensional bonding material.Type: GrantFiled: November 28, 2016Date of Patent: November 6, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Rinus T. P. Lee, Bharat V. Krishnan, Hui Zang, Matthew W. Stoker
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Publication number: 20180286863Abstract: The disclosure is directed to an integrated circuit structure. The integrated circuit structure may include: a first device region laterally adjacent to a second device region over a substrate, the first device region including a first fin and the second device region including a second fin; a first source/drain epitaxial region substantially surrounding at least a portion of the first fin; a spacer substantially surrounding the first source/drain epitaxial region, the spacer including an opening in a lateral end portion of the spacer such that the lateral end portion of the spacer overhangs a lateral end portion of the first source/drain epitaxial region; and a liner conformally coating the lateral end portion of the first source/drain epitaxial region beneath the overhanging lateral end portion of the spacer, wherein the liner includes an electrical insulator.Type: ApplicationFiled: June 7, 2018Publication date: October 4, 2018Inventors: Judson R. Holt, Christopher D. Sheraw, Timothy J. McArdle, Matthew W. Stoker, Mira Park, George R. Mulfinger, Yinxiao Yang
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Publication number: 20180197734Abstract: Reducing wormhole formation during n-type transistor fabrication includes providing a starting structure, the starting structure including a semiconductor substrate, a n-type source region and a n-type drain region of a transistor. The method further includes removing a portion of each of the n-type source region and the n-type drain region, the removing creating a source trench and a drain trench, and forming a buffer layer of silicon-based material(s) over the n-type source region and n-type drain region that is sufficiently thick to inhibit interaction between metal contaminants that may be present below surfaces of the n-type source trench and/or the n-type drain trench, and halogens subsequently introduced prior to source and drain formation. A resulting semiconductor structure is also provided.Type: ApplicationFiled: January 12, 2017Publication date: July 12, 2018Applicant: GLOBALFOUNDRIES Inc.Inventors: Bhupesh CHANDRA, Annie LEVESQUE, Matthew W. STOKER, Shreesh NARASIMHA, Viorel ONTALUS, Michael STEIGERWALT, Joshua BELL
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Patent number: 10020307Abstract: The disclosure is directed to an integrated circuit structure and a method of forming the same. The integrated circuit structure may include: a first device region laterally adjacent to a second device region over a substrate, the first device region including a first fin and the second device region including a second fin; a first source/drain epitaxial region substantially surrounding at least a portion of the first fin; a spacer substantially surrounding the first source/drain epitaxial region, the spacer including an opening in a lateral end portion of the spacer such that the lateral end portion of the spacer overhangs a lateral end portion of the first source/drain epitaxial region; and a liner lining the lateral end portion of the first source/drain epitaxial region beneath the overhanging lateral end portion of the spacer.Type: GrantFiled: February 10, 2017Date of Patent: July 10, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Judson R. Holt, Christopher D. Sheraw, Timothy J. McArdle, Matthew W. Stoker, Mira Park, George R. Mulfinger, Yinxiao Yang
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Publication number: 20180151449Abstract: One aspect of the disclosure is directed to a method of forming a semiconductor structure. The method including: removing each fin in a set of fins from between insulator pillars to expose a portion of a substrate between each insulator pillar, the substrate having a first device region and a second device region; forming a first material over the exposed portions of the substrate between each insulator pillar, the first material including a two-dimensional material; forming a second material over the first material in the first device region, the second material including a first three-dimensional bonding material; and forming a third material over the exposed first material in the second device region, the third material including a second three-dimensional bonding material.Type: ApplicationFiled: November 28, 2016Publication date: May 31, 2018Inventors: Rinus T. P. Lee, Bharat V. Krishnan, Hui Zang, Matthew W. Stoker
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Patent number: 9673295Abstract: A transistor contact structure and methods of making the same. The method includes forming a first semiconductor layer in a source/drain opening of a substrate, the first layer having a non-planar top surface; forming a second semiconductor layer directly on the first layer, the second layer having a defect density greater than the first layer; and forming a silicide region formed with the second layer, the silicide region having a non-planar interface with the first layer. A portion of the silicide interface may be higher than a top surface of the substrate and another portion may be below.Type: GrantFiled: May 27, 2014Date of Patent: June 6, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Annie Levesque, Viorel C. Ontalus, Matthew W. Stoker
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Patent number: 9287399Abstract: A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects.Type: GrantFiled: October 7, 2014Date of Patent: March 15, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bhupesh Chandra, Paul Chang, Gregory G. Freeman, Dechao Guo, Judson R. Holt, Arvind Kumar, Timothy J. McArdle, Shreesh Narasimha, Viorel Ontalus, Sangameshwar Saudari, Christopher D. Sheraw, Matthew W. Stoker
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Patent number: 9236477Abstract: Silicon-carbon alloy structures can be formed as inverted U-shaped structures around semiconductor fins by a selective epitaxy process. A planarization dielectric layer is formed to fill gaps among the silicon-carbon alloy structures. After planarization, remaining vertical portions of the silicon-carbon alloy structures constitute silicon-carbon alloy fins, which can have sublithographic widths. The semiconductor fins may be replaced with replacement dielectric material fins. In one embodiment, employing a patterned mask layer, sidewalls of the silicon-carbon alloy fins can be removed around end portions of each silicon-carbon alloy fin. An anneal is performed to covert surface portions of the silicon-carbon alloy fins into graphene layers. In one embodiment, each graphene layer can include only a horizontal portion in a channel region, and include a horizontal portion and sidewall portions in source and drain regions.Type: GrantFiled: February 17, 2014Date of Patent: January 12, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Jack O. Chu, Christos Dimitrakopoulos, Eric C. Harley, Judson R. Holt, Timothy J. McArdle, Matthew W. Stoker
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Publication number: 20150349068Abstract: A transistor contact structure and methods of making the same. The method includes forming a first semiconductor layer in a source/drain opening of a substrate, the first layer having a non-planar top surface; forming a second semiconductor layer directly on the first layer, the second layer having a defect density greater than the first layer; and forming a silicide region formed with the second layer, the silicide region having a non-planar interface with the first layer. A portion of the silicide interface may be higher than a top surface of the substrate and another portion may be below.Type: ApplicationFiled: May 27, 2014Publication date: December 3, 2015Applicant: International Business Machines CorporationInventors: Annie Levesque, Viorel C. Ontalus, Matthew W. Stoker
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Patent number: 9190406Abstract: Disposable gate structures are formed over semiconductor material portions, and source and drain regions can be formed in the semiconductor material portions. After formation of a planarization dielectric layer, one type of disposable gate structure can be removed selective to at least another type of disposable gate structure employing a patterned hard dielectric mask layer. After recessing a surface portion of a body portion, a heteroepitaxial channel portion is formed on the remaining physically exposed portion of the body portion by selective epitaxy of a semiconductor material different from the semiconductor material of the remaining body portion. A plurality of types of heteroepitaxial channel portions can be formed in different types of semiconductor devices. Replacement gate structures can be formed in the gate cavities to provide field effect transistors having different threshold voltages.Type: GrantFiled: January 20, 2014Date of Patent: November 17, 2015Assignee: International Business Machines CorporationInventors: Emre Alptekin, Wing L. Lai, Ravikumar Ramachandran, Matthew W. Stoker, Henry K. Utomo, Reinaldo A. Vega
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Publication number: 20150236147Abstract: Silicon-carbon alloy structures can be formed as inverted U-shaped structures around semiconductor fins by a selective epitaxy process. A planarization dielectric layer is formed to fill gaps among the silicon-carbon alloy structures. After planarization, remaining vertical portions of the silicon-carbon alloy structures constitute silicon-carbon alloy fins, which can have sublithographic widths. The semiconductor fins may be replaced with replacement dielectric material fins. In one embodiment, employing a patterned mask layer, sidewalls of the silicon-carbon alloy fins can be removed around end portions of each silicon-carbon alloy fin. An anneal is performed to covert surface portions of the silicon-carbon alloy fins into graphene layers. In one embodiment, each graphene layer can include only a horizontal portion in a channel region, and include a horizontal portion and sidewall portions in source and drain regions.Type: ApplicationFiled: February 17, 2014Publication date: August 20, 2015Applicant: International Business Machines CorporationInventors: Jack O. Chu, Christos Dimitrakopoulos, Eric C. Harley, Judson R. Holt, Timothy J. McArdle, Matthew W. Stoker
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Publication number: 20150206876Abstract: Disposable gate structures are formed over semiconductor material portions, and source and drain regions can be formed in the semiconductor material portions. After formation of a planarization dielectric layer, one type of disposable gate structure can be removed selective to at least another type of disposable gate structure employing a patterned hard dielectric mask layer. After recessing a surface portion of a body portion, a heteroepitaxial channel portion is formed on the remaining physically exposed portion of the body portion by selective epitaxy of a semiconductor material different from the semiconductor material of the remaining body portion. A plurality of types of heteroepitaxial channel portions can be formed in different types of semiconductor devices. Replacement gate structures can be formed in the gate cavities to provide field effect transistors having different threshold voltages.Type: ApplicationFiled: January 20, 2014Publication date: July 23, 2015Applicant: International Business Machines CorporationInventors: Emre Alptekin, Wing L. Lai, Ravikumar Ramachandran, Matthew W. Stoker, Henry K. Utomo, Reinaldo A. Vega
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Publication number: 20150097270Abstract: A method of forming a semiconductor structure includes forming a first fin in a p-FET device region of a semiconductor substrate and a second fin in an n-FET device region of the semiconductor substrate substantially parallel to the first fin. The first fin and the second fin each comprise a strained semiconductor material. Next, the second fin is amorphized to form a relaxed fin by implanting ions into the second fin while protecting the first fin.Type: ApplicationFiled: October 7, 2013Publication date: April 9, 2015Applicant: International Business Machines CorporationInventors: Stephen W. Bedell, Dominic J. Schepis, Matthew W. Stoker
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Publication number: 20150084096Abstract: A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects.Type: ApplicationFiled: October 7, 2014Publication date: March 26, 2015Inventors: Bhupesh Chandra, Paul Chang, Gregory G. Freeman, Dechao Guo, Judson R. Holt, Arvind Kumar, Timothy J. McArdle, Shreesh Narasimha, Viorel Ontalus, Sangameshwar Saudari, Christopher D. Sheraw, Matthew W. Stoker
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Patent number: 8940595Abstract: A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects.Type: GrantFiled: March 15, 2013Date of Patent: January 27, 2015Assignee: International Business Machines CorporationInventors: Bhupesh Chandra, Paul Chang, Gregory G. Freeman, Dechao Guo, Judson R. Holt, Arvind Kumar, Timothy J. McArdle, Shreesh Narasimha, Viorel Ontalus, Sangameshwar Rao Saudari, Christopher D. Sheraw, Matthew W. Stoker