Patents by Inventor Matthew Wordeman
Matthew Wordeman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20070235708Abstract: A programmable link structure for use in three dimensional integration (3DI) semiconductor devices includes a via filled at least in part with a phase change material (PCM) and a heating device proximate the PCM. The heating device is configured to switch the conductivity of a transformable portion of the PCM between a lower resistance crystalline state and a higher resistance amorphous state. Thereby, the via defines a programmable link between an input connection located at one end thereof and an output connection located at another end thereof.Type: ApplicationFiled: March 30, 2006Publication date: October 11, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bruce Elmegreen, Lia Krusin-Elbaum, Chung Lam, Dennis Newns, Matthew Wordeman, Albert Young
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Publication number: 20070235784Abstract: A switching circuit configured for controlling static power consumption in integrated circuits includes a plurality of three-terminal, phase change material (PCM) switching devices connected between a voltage supply terminal and a corresponding sub-block of integrated circuit logic. Each of the PCM switching devices further includes a PCM disposed in contact between a first terminal and a second terminal, a heating device disposed in contact between the second terminal and a third terminal, the heating device positioned proximate the PCM, and configured to switch the conductivity of a transformable portion of the PCM between a lower resistance crystalline state and a higher resistance amorphous state; and an insulating layer configured to electrically isolate the heater from said PCM material, and the heater from the first terminal.Type: ApplicationFiled: March 30, 2006Publication date: October 11, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lia Krusin-Elbaum, Dennis Newns, Matthew Wordeman
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Publication number: 20070223298Abstract: A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a local bit line; a first transistor having a control terminal connected to the local bit line, a first bias terminal connected to a first bank bit line of a given pair of bank bit lines, and a second bias terminal connecting to a first voltage source; a second transistor having a control terminal connected to a corresponding one of the block select lines, a first bias terminal connected to a second bank bit line of the given pair of bank bit lines, and a second bias terminal connected to the local bit line; and a plurality of memory cells connected to the local bit line and to respective word lines in the memory circuit.Type: ApplicationFiled: May 29, 2007Publication date: September 27, 2007Inventors: John Barth, Paul Parries, William Reohr, Matthew Wordeman
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Publication number: 20070025170Abstract: A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a local bit line; a first transistor having a control terminal connected to the local bit line, a first bias terminal connected to a first bank bit line of a given pair of bank bit lines, and a second bias terminal connecting to a first voltage source; a second transistor having a control terminal connected to a corresponding one of the block select lines, a first bias terminal connected to a second bank bit line of the given pair of bank bit lines, and a second bias terminal connected to the local bit line; and a plurality of memory cells connected to the local bit line and to respective word lines in the memory circuit.Type: ApplicationFiled: July 27, 2005Publication date: February 1, 2007Applicant: International Business Machines CorporationInventors: John Barth, Paul Parries, William Reohr, Matthew Wordeman
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Patent number: 6990025Abstract: A multi-port memory architecture utilizing an open bitline configuration for the read bitline is described. The memory is sub-divided into two arrays (A and B) consisting of memory gain cells arranged in a matrix formation, the cells having two general ports or separate read and write ports to enable simultaneous a read and write operation. Each memory array includes a reference wordline coupled to reference cells. When the reference cell is accessed, the read bitline (RBL) discharges to a level at half the value taken by a cell storing a 0 or 1. Each pair of RBLB in the same column of the two arrays is coupled to a differential sense amplifier, and each write bitline (WBL) in the two arrays is linked to write drivers WBLs in the two arrays are driven to the same voltage and at the same slew rate. The WBL swing in each array creates coupling noise by the bitline-to-bitline capacitors.Type: GrantFiled: August 29, 2003Date of Patent: January 24, 2006Assignee: International Business Machines CorporationInventors: Toshiaki Kirihata, Hoki Kim, Matthew Wordeman
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Publication number: 20050193253Abstract: Disclosed is a flexible command multiplication scheme for the built-in-self test (BIST) of a high-speed embedded memory array that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A stand-alone BIST logic controller operates at a lower frequency and communicates with a command multiplier using a low-speed BIST instruction seed set. The command multiplier uses offset or directive registers to drive a logic unit or ALU to generate ānā sets of CAD information which are then time-multiplexed to the embedded memory at a speed ānā times faster than the BIST operating speed.Type: ApplicationFiled: February 13, 2004Publication date: September 1, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jonathan Fales, Gregory Fredeman, Kevin Gorman, Mark Jacunski, Toshiaki Kirihata, Alan Norris, Paul Parries, Matthew Wordeman
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Publication number: 20050180230Abstract: A method for allocating redundancies during a multi-bank operation in a memory device which includes two or more redundancy domains is described. The method includes steps of enabling a pass/fail bit detection to activate a given bank. The pass/fail bit detection is prompted only for a selected domain and is disabled when it addresses other domains. By altering the domain selection, it is possible to enable a redundancy allocation for any domain regardless of the multi-bank operation. The method may preferably be realized by using a dynamic exclusive-OR logic with true and complement expected data pairs. When combined with simple pointer logic, the selection of domains may be generated internally, simplifying the built in self-test and other test control protocols, while at the same time tracking those that fail.Type: ApplicationFiled: February 12, 2004Publication date: August 18, 2005Inventors: Gregory Fredeman, Mark Jacunski, Toshiaki Kirihata, Matthew Wordeman
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Publication number: 20050047218Abstract: A multi-port memory architecture utilizing an open bitline configuration for the read bitline is described. The memory is sub-divided into two arrays (A and B) consisting of memory gain cells arranged in a matrix formation, the cells having two general ports or separate read and write ports to enable simultaneous a read and write operation. Each memory array includes a reference wordline coupled to reference cells. When the reference cell is accessed, the read bitline (RBL) discharges to a level at half the value taken by a cell storing a 0 or 1. Each pair of RBLB in the same column of the two arrays is coupled to a differential sense amplifier, and each write bitline (WBL) in the two arrays is linked to write drivers WBLs in the two arrays are driven to the same voltage and at the same slew rate. The WBL swing in each array creates coupling noise by the bitline-to-bitline capacitors.Type: ApplicationFiled: August 29, 2003Publication date: March 3, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toshiaki Kirihata, Hoki Kim, Matthew Wordeman
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Patent number: 6829682Abstract: A method for controlling the operation of a dynamic random access memory (DRAM) system, the DRAM system having a plurality of memory cells organized into rows and columns, is disclosed. In an exemplary embodiment of the invention, the method includes enabling a destructive read mode, the destructive read mode for destructively reading a bit of information stored within an addressed DRAM memory cell. The destructively read bit of information is temporarily stored into a temporary storage device. A delayed write back mode is enabled, the delayed write back mode for restoring the bit of information back to the addressed DRAM memory cell at a later time. The execution of the delayed write back mode is then scheduled, depending upon the availability of space within the temporary storage device.Type: GrantFiled: April 26, 2001Date of Patent: December 7, 2004Assignee: International Business Machines CorporationInventors: Toshiaki Kirihata, Sang Hoo Dhong, Hwa-Joon Oh, Matthew Wordeman
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Publication number: 20020161967Abstract: A method for controlling the operation of a dynamic random access memory (DRAM) system, the DRAM system having a plurality of memory cells organized into rows and columns, is disclosed. In an exemplary embodiment of the invention, the method includes enabling a destructive read mode, the destructive read mode for destructively reading a bit of information stored within an addressed DRAM memory cell. The destructively read bit of information is temporarily stored into a temporary storage device. A delayed write back mode is enabled, the delayed write back mode for restoring the bit of information back to the addressed DRAM memory cell at a later time. The execution of the delayed write back mode is then scheduled, depending upon the availability of space within the temporary storage device.Type: ApplicationFiled: April 26, 2001Publication date: October 31, 2002Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toshiaki Kirihata, Sang Hoo Dhong, Hwa-Joon Oh, Matthew Wordeman