Abstract: A method is disclosed for creating a netlist for the configuration of an FPGA, wherein the code of a first program comprises a multiplicity of subroutines. The code of the first program can be combined with the code of a second program to form a third program. A netlist for the configuration of an FPGA can be created from the third program, wherein at least one first subroutine of the first program is not used at the runtime of the third program. The first subroutine can be recognized in an automated manner, and a fourth program can be created on the basis of the first program. Also, the first subroutine can be removed during the creation of the fourth program, such that the fourth program does not contain the first subroutine.

Abstract: The present disclosure relates to a method for generating an overall netlist (50) comprising the following steps: providing a first PLD code (24) as first netlist (26), wherein the first PLD code (24) has at least one first functional block (28), providing a second PLD code (30), wherein the second PLD code (30) has at least one second functional block (32) for alternative use instead of a corresponding first functional block (28), providing a switch PLD code (40) having at least one switch (42) assigned to the at least one first functional block (28) for connecting the first functional block (28) assigned to the switch (42), connecting the at least one second functional block (32) to one switch from the at least one switch (42) as an alternative to the corresponding first functional block (28), implementing at least one switch driving signal (44) for the at least one second functional block (32), wherein the at least one switch driving signal (44) is assigned to the corresponding switch (42) for connecting t

Abstract: The present disclosure relates to a method for generating an overall netlist (50) comprising the following steps: providing a first PLD code (24) as first netlist (26), wherein the first PLD code (24) has at least one first functional block (28), providing a second PLD code (30), wherein the second PLD code (30) has at least one second functional block (32) for alternative use instead of a corresponding first functional block (28), providing a switch PLD code (40) having at least one switch (42) assigned to the at least one first functional block (28) for connecting the first functional block (28) assigned to the switch (42), connecting the at least one second functional block (32) to one switch from the at least one switch (42) as an alternative to the corresponding first functional block (28), implementing at least one switch driving signal (44) for the at least one second functional block (32), wherein the at least one switch driving signal (44) is assigned to the corresponding switch (42) for connecting t

Abstract: An arrangement for disabling a configuration of a first programmable hardware component, having the first programmable hardware component, a second programmable hardware component, and a switching element. The first programmable hardware component has a configuration interface for configuring a logic of the first programmable hardware component, a data interface for communication of the logic with the second programmable hardware component, a debugging interface for debugging and configuring the logic, and a configuration monitoring interface for signaling a configuration process of the logic. The switching element is designed and connected to the debugging interface such that access to the debugging interface during a configuration process of the logic can be disabled.

Abstract: An arrangement for the partial release of a debug interface of a programmable hardware component, whereby a first logic for the programmable hardware component can be stored in a configuration memory and a configuration device is designed to program the programmable hardware component via a configuration interface of the programmable hardware component according to the first logic. The configuration device is further designed to register a programming process of the programmable hardware component which occurs via the debug interface according to a second logic and, upon termination of the programming process occurring via the debug interface, reprograms the programmable hardware component according to the first logic.

Abstract: An arrangement for disabling a configuration of a first programmable hardware component, having the first programmable hardware component, a second programmable hardware component, and a switching element. The first programmable hardware component has a configuration interface for configuring a logic of the first programmable hardware component, a data interface for communication of the logic with the second programmable hardware component, a debugging interface for debugging and configuring the logic, and a configuration monitoring interface for signaling a configuration process of the logic. The switching element is designed and connected to the debugging interface such that access to the debugging interface during a configuration process of the logic can be disabled.

Abstract: An arrangement for the partial release of a debug interface of a programmable hardware component, whereby a first logic for the programmable hardware component can be stored in a configuration memory and a configuration device is designed to program the programmable hardware component via a configuration interface of the programmable hardware component according to the first logic. The configuration device is further designed to register a programming process of the programmable hardware component which occurs via the debug interface according to a second logic and, upon termination of the programming process occurring via the debug interface, reprograms the programmable hardware component according to the first logic.