Abstract: A driver circuit arrangement for driving a transistor bridge, which includes at least a first half-bridge composed of a low-side transistor and a high-side transistor, is described herein. In accordance with one example of the description, the circuit includes a current source and a detection circuit. The current source is operably coupled to the high-side transistor of the first half-bridge and configured to supply a test current to the first half bridge. The detection circuit is configured to compare a voltage sense signal, which represents the voltage across the high-side transistor of the first half-bridge, with at least one first threshold to detect, dependent on the result of this comparison, whether a short-circuit is present in the first half-bridge.

Abstract: In accordance with an embodiment, a method includes generating a clock signal; generating a switching signal based on the clock signal; generating a synchronization signal having an edge transition corresponding to a predetermined phase of the switching signal; transmitting the synchronization signal to a master controller; receiving a frequency adjustment command from the master controller based on the transmitted synchronization signal; and adjusting a frequency of the clock signal based on the frequency adjustment command.

Abstract: In accordance with an embodiment, a method includes driving a predetermined load using a driver circuit according to a drive pattern; supplying power to the driver circuit using a switched-mode power supply (SMPS) configured to be coupled to at least one external component; and verifying functionality of the SMPS while driving the predetermined load. Verifying the functionality includes monitoring at least one operating parameter of the SMPS, where the at least one operating parameter of the SMPS is dependent on the drive pattern and the at least one external component, comparing the at least one operating parameter to at least one expected operating parameter to form a first comparison result, and indicating an error condition based on the first comparison result.

Abstract: In accordance with an embodiment, a method includes using a monitoring circuit disposed on a monolithic integrated circuit to monitor an output signal of a first switching transistor for a first output edge transition at a monitoring terminal of the monolithic integrated circuit; using a time measuring circuit disposed on the monolithic integrated circuit to measure a first time delay between a first input edge transition of a first drive signal and the first output edge transition, where the first drive signal is configured to cause a change of state of the first switching transistor; using an analysis circuit disposed on the monolithic integrated circuit to compare the measured first time delay with a first predetermined threshold to form a first comparison result; and indicating a first error condition based on the first comparison result.

Abstract: In accordance with an embodiment, a method includes monitoring a first voltage across a buffer capacitor; activating a first current path between a power supply node and the buffer capacitor when the monitored first voltage is below a first threshold voltage, activating a second current path between the power supply node and the buffer capacitor when the monitored first voltage is below a second threshold voltage, and transferring power from the buffer capacitor to a driver circuit coupled across the buffer capacitor.

Abstract: In accordance with an embodiment, a method includes using a monitoring circuit disposed on a monolithic integrated circuit to monitor an output signal of a first switching transistor for a first output edge transition at a monitoring terminal of the monolithic integrated circuit; using a time measuring circuit disposed on the monolithic integrated circuit to measure a first time delay between a first input edge transition of a first drive signal and the first output edge transition, where the first drive signal is configured to cause a change of state of the first switching transistor; using an analysis circuit disposed on the monolithic integrated circuit to compare the measured first time delay with a first predetermined threshold to form a first comparison result; and indicating a first error condition based on the first comparison result.

Abstract: A driver circuit arrangement for driving a transistor bridge, which includes at least a first half-bridge composed of a low-side transistor and a high-side transistor, is described herein. In accordance with one example of the description, the circuit includes a current source and a detection circuit. The current source is operably coupled to the high-side transistor of the first half-bridge and configured to supply a test current to the first half bridge. The detection circuit is configured to compare a voltage sense signal, which represents the voltage across the high-side transistor of the first half-bridge, with at least one first threshold to detect, dependent on the result of this comparison, whether a short-circuit is present in the first half-bridge.

Abstract: A driver circuit arrangement for driving a transistor bridge, which includes at least a first half-bridge composed of a low-side transistor and a high-side transistor, is described herein. In accordance with one example of the description, the circuit includes a current source and a detection circuit. The current source is operably coupled to the high-side transistor of the first half-bridge and configured to supply a test current to the first half bridge. The detection circuit is configured to compare a voltage sense signal, which represents the voltage across the high-side transistor of the first half-bridge, with at least one first threshold to detect, dependent on the result of this comparison, whether a short-circuit is present in the first half-bridge.

Abstract: Supply voltage switching circuitry that is configured to dynamically switch between a battery supply voltage and a boost supply voltage, that is generated from the battery supply voltage, to power half-bridge driver circuitry based on an on-going evaluation of one or more system parameters. The supply voltage switching circuitry is configured to deliver the boost supply voltage to high-side driver circuitry. The supply voltage switching circuitry is configured to select between delivering the boost supply voltage to low-side driver circuitry and delivering the battery supply voltage to low-side driver circuitry.

Abstract: A method includes applying a current to an input pin of an integrated circuit; converting an analog signal at the input pin to a digital stream using a Sigma-Delta modulator; converting the digital stream to a first digital output signal proportional to the analog signal in a first input range between a first analog signal value and a second analog signal value, where the first input range corresponds to a pre-determined range of the analog signal smaller than a full-scale input range of the analog signal; converting the digital stream to a second output signal; comparing the second output signal to a first threshold corresponding to a third analog signal value at the input pin that is outside of the first input range; and providing an indication of an open circuit condition at the input pin when the second output signal crosses the first threshold.

Abstract: In accordance with an embodiment, a method includes generating a clock signal; generating a switching signal based on the clock signal; generating a synchronization signal having an edge transition corresponding to a predetermined phase of the switching signal; transmitting the synchronization signal to a master controller; receiving a frequency adjustment command from the master controller based on the transmitted synchronization signal; and adjusting a frequency of the clock signal based on the frequency adjustment command.

Abstract: A drive circuit includes an internal oscillator and a pre-drive controller coupled to the internal oscillator. The pre-drive controller can have a switch control output configured to be coupled to a switch input. The pre-drive controller can receive switch control data, receive a clock signal, receive a synchronization signal, synchronize the internal oscillator based on the clock signal and the synchronization signal, and generate a pulse modulated switching signal at the switch control output based on the switch control data and the internal oscillator.

Abstract: Supply voltage switching circuitry that is configured to dynamically switch between a battery supply voltage and a boost supply voltage, that is generated from the battery supply voltage, to power half-bridge driver circuitry based on an on-going evaluation of one or more system parameters.

Abstract: A drive circuit includes an internal oscillator and a pre-drive controller coupled to the internal oscillator. The pre-drive controller can have a switch control output configured to be coupled to a switch input. The pre-drive controller can receive switch control data, receive a clock signal, receive a synchronization signal, synchronize the internal oscillator based on the clock signal and the synchronization signal, and generate a pulse modulated switching signal at the switch control output based on the switch control data and the internal oscillator.

Abstract: A driver circuit arrangement for driving a transistor bridge, which includes at least a first half-bridge composed of a low-side transistor and a high-side transistor, is described herein. In accordance with one example of the description, the circuit includes a current source and a detection circuit. The current source is operably coupled to the high-side transistor of the first half-bridge and configured to supply a test current to the first half bridge. The detection circuit is configured to compare a voltage sense signal, which represents the voltage across the high-side transistor of the first half-bridge, with at least one first threshold to detect, dependent on the result of this comparison, whether a short-circuit is present in the first half-bridge.

Abstract: In some embodiments, a method of operating a sigma-delta analog-to-digital converter (ADC) includes converting an analog input signal into a sequence of digital data using a sigma-delta modulator of the sigma-delta ADC, setting a first configuration for a decimation filter of the sigma-delta ADC according to a first condition of a measurement window, filtering the sequence of digital data using a low-pass filter (LPF) of the decimation filter, and in response to a change in the measurement window, setting a second configuration for the decimation filter according to a second condition of the measurement window.

Abstract: Systems and techniques are described for monitoring the operating temperature of one or more circuit elements, such as a metal oxide field effect transistor (MOSFET) switch, where the circuit element is used to control at least one phase of an electric motor. The systems and techniques may calculate temperature by determining at least two electrical signals from the circuit element taken at least two different times. This results in an accurate temperature calculation without requiring precise knowledge of the particular characteristics of each respective circuit element.

Abstract: Systems and techniques are described for monitoring the operating temperature of one or more circuit elements, such as a metal oxide field effect transistor (MOSFET) switch, where the circuit element is used to control at least one phase of an electric motor. The systems and techniques may calculate temperature by determining at least two electrical signals from the circuit element taken at least two different times. This results in an accurate temperature calculation without requiring precise knowledge of the particular characteristics of each respective circuit element.

Abstract: In various embodiments a circuit arrangement is provided, having a bridge circuit including at least two switches connected in series; a bridge node which may provide a phase voltage arranged between the at least two switches; an electric motor having at least one phase winding coupled with the bridge node; a decoupling switch; a controller, wherein in an error case the controller may be configured to switch off the at least two switches, to determine whether a predefined condition is satisfied, and to one of delayed switching off the decoupling switch; and switching off the at least two switches and the decoupling switch simultaneously, depending upon whether the predefined condition is satisfied; wherein the controller may determine that the predefined condition is satisfied when the decoupling switch may be switched off without damage from the current applied to it when the at least two switches are switched off.

Abstract: In various embodiments a circuit arrangement is provided, having a bridge circuit including at least two switches connected in series; a bridge node which may provide a phase voltage arranged between the at least two switches; an electric motor having at least one phase winding coupled with the bridge node; a decoupling switch; a controller, wherein in an error case the controller may be configured to switch off the at least two switches, to determine whether a predefined condition is satisfied, and to one of delayed switching off the decoupling switch; and switching off the at least two switches and the decoupling switch simultaneously, depending upon whether the predefined condition is satisfied; wherein the controller may determine that the predefined condition is satisfied when the decoupling switch may be switched off without damage from the current applied to it when the at least two switches are switched off.