Patents by Inventor Matthias Dinter
Matthias Dinter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8863053Abstract: A system generally including a clock structure analysis tool, a static timing analysis tool and a waveform tool is disclosed. The clock structure analysis tool may be configured to generate a simplified clock structure for a clock signal in a complex clock structure in a design of a circuit. The static timing analysis tool may be configured to generate a plurality of results for a plurality of intermediate signals in the simplified clock structure in response to a static timing analysis of the design. The waveform tool may be configured to generate a first representation in a graphical user interface format of the intermediate signals and the results.Type: GrantFiled: August 27, 2013Date of Patent: October 14, 2014Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Juergen Dirks, Martin Fennell, Matthias Dinter
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Publication number: 20130346932Abstract: A system generally including a clock structure analysis tool, a static timing analysis tool and a waveform tool is disclosed. The clock structure analysis tool may be configured to generate a simplified clock structure for a clock signal in a complex clock structure in a design of a circuit. The static timing analysis tool may be configured to generate a plurality of results for a plurality of intermediate signals in the simplified clock structure in response to a static timing analysis of the design. The waveform tool may be configured to generate a first representation in a graphical user interface format of the intermediate signals and the results.Type: ApplicationFiled: August 27, 2013Publication date: December 26, 2013Applicant: LSI CorporationInventors: Juergen Dirks, Martin Fennell, Matthias Dinter
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Patent number: 8584068Abstract: A storage medium for use in a computer to develop a circuit design. The storage medium recording a software tool that may be readable and executable by the computer. The software tool generally includes the steps of (A) receiving a first user input that identifies a specific cell of a plurality of existing cells in the circuit design, the specific cell having a timing characteristic, (B) generating a replacement display corresponding to the specific cell, the replacement display comprising a plurality of alternate cells suitable to replace the specific cell, each of the alternate cells having a different value associated with the timing characteristic of the specific cell, (C) receiving a second user input that identifies a replacement cell of the alternate cells and (D) automatically generating a first engineering change order to replace the specific cell with the replacement cell.Type: GrantFiled: May 13, 2010Date of Patent: November 12, 2013Assignee: LSI CorporationInventors: Matthias Dinter, Juergen Dirks, Herbert Johannes Preuthen
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Patent number: 8572543Abstract: A method for designing an integrated circuit is disclosed. The method generally comprises the steps of (A) splitting a design layout of the integrated circuit into a plurality of tiles, (B) adding a plurality of tie-to cells to the design layout, wherein at least one of the tie-to cells generating a tie-to signal at a particular logical level is added into each of the tiles having at least one gate with an input fixed to the particular logical level and (C) routing the tie-to signal to each of the inputs within each of the tiles.Type: GrantFiled: April 9, 2012Date of Patent: October 29, 2013Assignee: LSI CorporationInventors: Juergen Dirks, Matthias Dinter, Ralf Leuchter
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Patent number: 8539407Abstract: A system generally including a clock structure analysis tool, a static timing analysis tool and a waveform tool is disclosed. The clock structure analysis tool may be configured to generate a simplified clock structure for a clock signal in a complex clock structure in a design of a circuit. The static timing analysis tool may be configured to generate a plurality of results for a plurality of intermediate signals in the simplified clock structure in response to a static timing analysis of the design. The waveform tool may be configured to generate a first representation in a graphical user interface format of the intermediate signals and the results.Type: GrantFiled: February 19, 2009Date of Patent: September 17, 2013Assignee: LSI CorporationInventors: Juergen Dirks, Martin Fennell, Matthias Dinter
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Patent number: 8332801Abstract: A method for correcting a plurality of violations in a circuit design and new cells used in the method are disclosed. The method generally includes the steps of (A) implementing a first engineering change order in the circuit design to correct a first of the violations, (B) implementing a second engineering change order with a special cell to correct a second of the violations, the special cell having a plurality of interfaces available for a signal path associated with the second violation, each of the interfaces having a characteristic appropriate to correct the second violation, each of the characteristics having a different performance and (C) routing the signal path to one of the interfaces to fix the second violation.Type: GrantFiled: October 29, 2009Date of Patent: December 11, 2012Assignee: LSI CorporationInventors: Juergen Dirks, Matthias Dinter, Johann Leyrer
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Publication number: 20120198407Abstract: A method for designing an integrated circuit is disclosed. The method generally comprises the steps of (A) splitting a design layout of the integrated circuit into a plurality of tiles, (B) adding a plurality of tie-to cells to the design layout, wherein at least one of the tie-to cells generating a tie-to signal at a particular logical level is added into each of the tiles having at least one gate with an input fixed to the particular logical level and (C) routing the tie-to signal to each of the inputs within each of the tiles.Type: ApplicationFiled: April 9, 2012Publication date: August 2, 2012Inventors: Juergen Dirks, Matthias Dinter, Ralf Leuchter
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Patent number: 8161447Abstract: A method for designing an integrated circuit is disclosed. The method generally comprises the steps of (A) splitting a design layout of the integrated circuit into a plurality of tiles, (B) adding a plurality of tie-to cells to the design layout, wherein at least one of the tie-to cells generating a tie-to signal at a particular logical level is added into each of the tiles having at least one gate with an input fixed to the particular logical level and (C) routing the tie-to signal to each of the inputs within each of the tiles.Type: GrantFiled: May 11, 2009Date of Patent: April 17, 2012Assignee: LSI CorporationInventors: Juergen Dirks, Matthias Dinter, Ralf Leuchter
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Publication number: 20100229141Abstract: A storage medium for use in a computer to develop a circuit design. The storage medium recording a software tool that may be readable and executable by the computer. The software tool generally includes the steps of (A) receiving a first user input that identifies a specific cell of a plurality of existing cells in the circuit design, the specific cell having a timing characteristic, (B) generating a replacement display corresponding to the specific cell, the replacement display comprising a plurality of alternate cells suitable to replace the specific cell, each of the alternate cells having a different value associated with the timing characteristic of the specific cell, (C) receiving a second user input that identifies a replacement cell of the alternate cells and (D) automatically generating a first engineering change order to replace the specific cell with the replacement cell.Type: ApplicationFiled: May 13, 2010Publication date: September 9, 2010Inventors: Matthias Dinter, Juergen Dirks, Herbert Johannes Preuthen
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Patent number: 7747975Abstract: A storage medium for use in a computer to develop a circuit design. The storage medium recording a software tool that may be readable and executable by the computer. The software tool generally includes the steps of (A) receiving a first user input that identifies a specific cell of a plurality of existing cells in the circuit design, the specific cell having a timing characteristic, (B) generating a replacement display corresponding to the specific cell, the replacement display comprising a plurality of alternate cells suitable to replace the specific cell, each of the alternate cells having a different value associated with the timing characteristic of the specific cell, (C) receiving a second user input that identifies a replacement cell of the alternate cells and (D) automatically generating a first engineering change order to replace the specific cell with the replacement cell.Type: GrantFiled: November 28, 2007Date of Patent: June 29, 2010Assignee: LSI CorporationInventors: Matthias Dinter, Juergen Dirks, Herbert Johannes Preuthen
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Publication number: 20100050142Abstract: A method for correcting a plurality of violations in a circuit design and new cells used in the method are disclosed. The method generally includes the steps of (A) implementing a first engineering change order in the circuit design to correct a first of the violations, (B) implementing a second engineering change order with a special cell to correct a second of the violations, the special cell having a plurality of interfaces available for a signal path associated with the second violation, each of the interfaces having a characteristic appropriate to correct the second violation, each of the characteristics having a different performance and (C) routing the signal path to one of the interfaces to fix the second violation.Type: ApplicationFiled: October 29, 2009Publication date: February 25, 2010Inventors: Juergen Dirks, Matthias Dinter, Johann Leyrer
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Patent number: 7634748Abstract: A method for correcting a plurality of violations in a circuit design and new cells used in the method are disclosed. The method generally includes the steps of (A) implementing a first engineering change order in the circuit design to correct a first of the violations, (B) implementing a second engineering change order with a special cell to correct a second of the violations, the special cell having a plurality of interfaces available for a signal path associated with the second violation, each of the interfaces having a characteristic appropriate to correct the second violation, each of the characteristics having a different performance and (C) routing the signal path to one of the interfaces to fix the second violation.Type: GrantFiled: July 22, 2004Date of Patent: December 15, 2009Assignee: LSI CorporationInventors: Juergen Dirks, Matthias Dinter, Johann Leyrer
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Publication number: 20090228855Abstract: A method for designing an integrated circuit is disclosed. The method generally comprises the steps of (A) splitting a design layout of the integrated circuit into a plurality of tiles, (B) adding a plurality of tie-to cells to the design layout, wherein at least one of the tie-to cells generating a tie-to signal at a particular logical level is added into each of the tiles having at least one gate with an input fixed to the particular logical level and (C) routing the tie-to signal to each of the inputs within each of the tiles.Type: ApplicationFiled: May 11, 2009Publication date: September 10, 2009Inventors: Juergen Dirks, Matthias Dinter, Ralf Leuchter
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Publication number: 20090150846Abstract: A system generally including a clock structure analysis tool, a static timing analysis tool and a waveform tool is disclosed. The clock structure analysis tool may be configured to generate a simplified clock structure for a clock signal in a complex clock structure in a design of a circuit. The static timing analysis tool may be configured to generate a plurality of results for a plurality of intermediate signals in the simplified clock structure in response to a static timing analysis of the design. The waveform tool may be configured to generate a first representation in a graphical user interface format of the intermediate signals and the results.Type: ApplicationFiled: February 19, 2009Publication date: June 11, 2009Inventors: Juergen Dirks, Martin Fennell, Matthias Dinter
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Patent number: 7546568Abstract: A method for designing an integrated circuit is disclosed. The method generally comprises the steps of (A) splitting a design layout of the integrated circuit into a plurality of tiles, (B) adding a plurality of tie-to cells to the design layout, wherein at least one of the tie-to cells generating a tie-to signal at a particular logical level is added into each of the tiles having at least one gate with an input fixed to the particular logical level and (C) routing the tie-to signal to each of the inputs within each of the tiles.Type: GrantFiled: December 19, 2005Date of Patent: June 9, 2009Assignee: LSI CorporationInventors: Juergen Dirks, Matthias Dinter, Ralf Leuchter
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Patent number: 7523426Abstract: A system generally including a clock structure analysis tool, a static timing analysis tool and a waveform tool is disclosed. The clock structure analysis tool may be configured to generate a simplified clock structure for a clock signal in a complex clock structure in a design of a circuit. The static timing analysis tool may be configured to generate a plurality of results for a plurality of intermediate signals in the simplified clock structure in response to a static timing analysis of the design. The waveform tool may be configured to generate a first representation in a graphical user interface format of the intermediate signals and the results.Type: GrantFiled: March 29, 2005Date of Patent: April 21, 2009Assignee: LSI CorporationInventors: Juergen Dirks, Martin Fennell, Matthias Dinter
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Patent number: 7398489Abstract: A method for establishing standard cell power connections is disclosed. The method generally includes the steps of (A) calculating a power consumption of a plurality of logic cells receiving power directly from a power rail, (B) removing at least one excess via from a plurality of vias directly connecting the power rail to a power mesh in response to the power consumption and (C) routing a signal through an area where the at least one excess via was removed.Type: GrantFiled: April 6, 2005Date of Patent: July 8, 2008Assignee: LSI CorporationInventors: Matthias Dinter, Juergen Dirks, Herbert Johannes Preuthen
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Publication number: 20080077903Abstract: A storage medium for use in a computer to develop a circuit design. The storage medium recording a software tool that may be readable and executable by the computer. The software tool generally includes the steps of (A) receiving a first user input that identifies a specific cell of a plurality of existing cells in the circuit design, the specific cell having a timing characteristic, (B) generating a replacement display corresponding to the specific cell, the replacement display comprising a plurality of alternate cells suitable to replace the specific cell, each of the alternate cells having a different value associated with the timing characteristic of the specific cell, (C) receiving a second user input that identifies a replacement cell of the alternate cells and (D) automatically generating a first engineering change order to replace the specific cell with the replacement cell.Type: ApplicationFiled: November 28, 2007Publication date: March 27, 2008Inventors: Matthias Dinter, Juergen Dirks, Herbert Preuthen
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Patent number: 7334206Abstract: A library cell, a method and/or a system for adding the cell to a circuit is disclosed. The method generally comprises a first step for generating a final layout of the cell having an area of interest in at least one upper layer within a first layer stack used for the circuit, the first layer stack including at most all of a plurality of physical layers available for fabrication. A second step may include placing the final layout in the circuit. A third step may route a network of the circuit through the cell using the at least one upper layer and avoiding the area of interest according to at least one of a plurality of rules.Type: GrantFiled: December 13, 2004Date of Patent: February 19, 2008Assignee: LSI Logic CorporationInventors: Matthias Dinter, Juergen Dirks, Roland Klemt
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Patent number: 7331028Abstract: A method and apparatus for managing a plurality of change orders for a circuit design is disclosed. The method generally includes the steps of (A) receiving the change orders generated manually by a user, (B) analyzing the circuit design with all of the change orders implemented and (C) generating a report suitable for the user to understand based on a result of the analyzing.Type: GrantFiled: July 30, 2004Date of Patent: February 12, 2008Assignee: LSI Logic CorporationInventors: Matthias Dinter, Juergen Dirks, Herbert Johannes Preuthen