Patents by Inventor Matthias FÜGGER

Matthias FÜGGER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Delay element, delay element chain and fast all-digital clock frequency adaptation circuit for voltage droop tolerance
    Patent number: 11520370
    Abstract: A circuit for delaying an electric signal (CI), comprises an input for the electric signal (CI); an input for a control signal (EI); a first storage element (U5) for storing the control signal; a delay element for delaying the electric signal; and an output for the delayed electric signal (CO). According to the invention, the electric signal is delayed, based on the stored control signal. The delay circuit is employed in a fast all-digital clock frequency adaptation circuit for voltage droop tolerance.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: December 6, 2022
    Assignee: Max-Planck-Gesellschaft zur Förderung der Wissenschaften E.V.
    Inventors: Christoph Lenzen, Matthias Függer, Ben Wiederhake, Attila Kinali, Mordechai Medina
  • DELAY ELEMENT, DELAY ELEMENT CHAIN AND FAST ALL-DIGITAL CLOCK FREQUENCY ADAPTATION CIRCUIT FOR VOLTAGE DROOP TOLERANCE
    Publication number: 20210089073
    Abstract: A circuit for delaying an electric signal (CI), comprises an input for the electric signal (CI); an input for a control signal (EI); a first storage element (U5) for storing the control signal; a delay element for delaying the electric signal; and an output for the delayed electric signal (CO). According to the invention, the electric signal is delayed, based on the stored control signal. The delay circuit is employed in a fast all-digital clock frequency adaptation circuit for voltage droop tolerance.
    Type: Application
    Filed: March 11, 2019
    Publication date: March 25, 2021
    Inventors: Christoph LENZEN, Matthias FÜGGER, Ben WIEDERHAKE, Attila KINALI
  • Efficient and dependable clock synchronization in hardware
    Patent number: 10411720
    Abstract: The invention comprises a fault-tolerant clock synchronization method with high precision, hardware implementations thereof and the corresponding digital circuits, designed to contain metastability.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: September 10, 2019
    Assignee: MAX-PLANCK-GESELLSCHAFT ZUR FÖRDERUNG DER WISSENSCHAFTEN E.V.
    Inventors: Christoph Lenzen, Matthias Függer, Attila Kinali, Stephan Friedrichs, Moti Medina
  • EFFICIENT AND DEPENDABLE CLOCK SYNCHRONIZATION IN HARDWARE
    Publication number: 20180351564
    Abstract: The invention comprises a fault-tolerant clock synchronization method with high precision, hardware implementations thereof and the corresponding digital circuits, designed to contain metastability.
    Type: Application
    Filed: June 12, 2018
    Publication date: December 6, 2018
    Inventors: Christoph LENZEN, Matthias FÜGGER, Attila KINALI, Stephan FRIEDRICHS, Moti MEDINA