Patents by Inventor Matthias Gruenewald

Matthias Gruenewald has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory access unit and method including generating memory selects to concurrently access a plurality of memories in a multi-dimensional array
    Patent number: 10592406
    Abstract: A memory access unit for handling transfers of samples in a d-dimensional array between a one of m data buses, where m?1, and k*m memories, where k?2, is disclosed. The memory access unit comprises k address calculators, each address calculator configured to receive a bus address to add a respective offset to generate a sample bus address and to generate, from the sample bus address according to an addressing scheme, a respective address in each of the d dimensions for access along one of the dimensions from the bus address according to an addressing scheme, for accessing a sample. The memory access unit comprises k sample collectors, each sample collector operable to generate a memory select for a one of the k*m memories so as to transfer the sample between a predetermined position in a bus data word and the respective one of the k*m memories.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: March 17, 2020
    Assignee: RENESAS ELECTRONICS EUROPE GMBH
    Inventor: Matthias Gruenewald
  • MEMORY ACCESS UNIT
    Publication number: 20170329702
    Abstract: A memory access unit for handling transfers of samples in a d-dimensional array between a one of m data buses, where m?1, and k*m memories, where k?2, is disclosed. The memory access unit comprises k address calculators, each address calculator configured to receive a bus address to add a respective offset to generate a sample bus address and to generate, from the sample bus address according to an addressing scheme, a respective address in each of the d dimensions for access along one of the dimensions from the bus address according to an addressing scheme, for accessing a sample. The memory access unit comprises k sample collectors, each sample collector operable to generate a memory select for a one of the k*m memories so as to transfer the sample between a predetermined position in a bus data word and the respective one of the k*m memories.
    Type: Application
    Filed: October 15, 2015
    Publication date: November 16, 2017
    Inventor: Matthias Gruenewald