Abstract: Various embodiments include a method for producing electronic assemblies. The method may include: applying a fluid printing medium in a structured manner using a printing device multiple times consecutively in a sequential series of individual printing steps; measuring a rheological property of the printing medium in an automated repeated series of individual measurement steps during or between the individual printing steps; executing a computer-implemented rheological model for the execution of the individual printing steps, using the repeatedly measured rheological property as a variable input parameter; determining a favorable value for a selected printing parameter with the rheological model based on the currently measured rheological property; and automatically setting the determined favorable value for the selected printing parameter.

Abstract: Various embodiments of the teachings herein include an apparatus comprising: a component; a cooling element; and a connecting element arranged between the component and the cooling element to thermally couple the cooling element to the component. The connecting element comprises a porous connecting body including a metal material. Pores of the connecting body are at least in part filled with a filling material including a low-melting alloy or a fluorinated organic liquid.

Abstract: Various embodiments of the teachings herein include a computer-implemented method for generating an identification data set for an electronic module having a substrate, a joint, and an electronic component. An example method includes: providing a digital and/or X-ray recording of at least a partial region of the module; and generating the identification data set based on at least a portion of the recording, the portion including the joint. The identification data set identifies at least one of a number, an arrangement, and/or a size of gas inclusions in the joint.

Abstract: The invention relates to a circuit arrangement, comprising at least one wiring carrier plate (1), characterized by at least one separating element (2) formed in the wiring carrier plate (1), which separating element divides the wiring carrier plate (1) into sections separated by the separating element (2), wherein the transfer of vibrations from one section to another section is at least partially decoupled and/or damped by the separating element (2). The invention further relates to a converter having such a circuit arrangement, and to an aircraft having a converter. The converter can comprise capacitor stacks (3) arranged on the wiring carrier plate (1), and power semiconductors (6).

Abstract: Various embodiments include a method for installing an electronic assembly having a die and a substrate with a reference plane. The method may include: providing a product carrier having recesses with varying dimensions different from one another; and arranging planar molded parts, joining materials, and the die on the product carrier. The die is in electrical contact with at least one planar molded part and at least one joining material. The method further includes forming functional elements from the planar molded parts and/or the die and the joining materials, the functional elements supporting the substrate and electrically contacting the reference plane.

Abstract: Various embodiments include a capacitor structure comprising: a plurality of capacitors disposed in a support structure, wherein each of the plurality of capacitors includes a first capacitor electrode and a second capacitor electrode. The support structure includes a first electrode and a second electrode. Each of the plurality of capacitors makes electrical contact with the first electrode via the respective first capacitor electrode and with the second electrode via the respective second capacitor electrode. The support structure includes a mounting side for surface mounting, the mounting side comprising a first contact area of the first electrode and a second contact area of the second electrode. The support structure defines a cuboid interior and the capacitors are disposed in the cuboid interior. An outer side of the support structure defines an additional structural framework outside the mounting side.

Abstract: Various embodiments of the teachings herein include power electronic circuits comprising: interconnected power modules, each with a power electronic element and a plurality of capacitors in parallel. The power electronic elements are mounted on a first side of substrate plates. The capacitors are mounted in a plurality of planes one above the other on a second side of the substrate plates. The substrate plates, with the power electronic elements forward and alongside each other, are fixed onto an assembly side of a base circuit carrier.

Abstract: Various embodiments include a circuit carrier comprising: an installation place for an electronic component; and a deposit of a joining adjuvant applied to the installation place. The installation place has at an edge, a recess forming a depression in a surface of the circuit carrier. The deposit comprises a sintered material with a protuberance at an edge of the deposit.

Abstract: Various embodiments of the teachings herein include power electronic circuits comprising: interconnected power modules, each with a power electronic element and a plurality of capacitors in parallel. The power electronic elements are mounted on a first side of substrate plates. The capacitors are mounted in a plurality of planes one above the other on a second side of the substrate plates. The substrate plates, with the power electronic elements forward and alongside each other, are fixed onto an assembly side of a base circuit carrier.

Abstract: The invention relates to a circuit arrangement, comprising at least one wiring carrier plate (1), characterized by at least one separating element (2) formed in the wiring carrier plate (1), which separating element divides the wiring carrier plate (1) into sections separated by the separating element (2), wherein the transfer of vibrations from one section to another section is at least partially decoupled and/or damped by the separating element (2). The invention further relates to a converter having such a circuit arrangement, and to an aircraft having a converter. The converter can comprise capacitor stacks (3) arranged on the wiring carrier plate (1), and power semiconductors (6).

Abstract: Various embodiments include a capacitor structure comprising: a plurality of capacitors disposed in a support structure, wherein each of the plurality of capacitors includes a first capacitor electrode and a second capacitor electrode. The support structure includes a first electrode and a second electrode. Each of the plurality of capacitors makes electrical contact with the first electrode via the respective first capacitor electrode and with the second electrode via the respective second capacitor electrode. The support structure includes a mounting side for surface mounting, the mounting side comprising a first contact area of the first electrode and a second contact area of the second electrode. The support structure defines a cuboid interior and the capacitors are disposed in the cuboid interior. An outer side of the support structure defines an additional structural framework outside the mounting side.

Abstract: A circuit arrangement is disclosed herein. The circuit arrangement includes a circuit carrier board, a power semiconductor arranged on the underside of the circuit carrier board, and a wiring carrier board arranged underneath the power semiconductor. The circuit arrangement further includes a metallic first spacer element arranged between the circuit carrier board and the wiring carrier board and via which an electric load current from the power semiconductor flows, wherein the first spacer element acts as a shunt through which current flows. The circuit arrangement further includes a voltage measuring unit, by which a voltage drop across the first spacer element, produced by the load current flow, may be determined. A converter having such a circuit arrangement, an aircraft having a converter, and a method for current measurement in power semiconductors are likewise specified.

Abstract: A solar cell includes a semiconductor wafer, at least one dielectric layer arranged on the semiconductor wafer, a metal layer arranged on the dielectric layer, and a contact structure arranged in the dielectric layer such that the contact structure provides an electrical connection between the metal layer and the semiconductor wafer. The contact structure has at least one first structure having a minimum dimension and at least one second structure having a maximum dimension, wherein the minimum dimension and the maximum dimension are defined along a surface of the semiconductor wafer and the minimum dimension of the first structure is greater than the maximum dimension of the second structure.

Abstract: A solar module having at least one solar cell on the rear-side surface of which a metallization layer is formed, and having a further solar cell, which is electrically connected to the solar cell by means of a conductive connector, the rear-side surface of the solar cell having at least one first surface region, at which the metallization layer is formed with a first layer thickness, and a second surface region, at which the metallization layer has an opening or is formed with a second layer thickness, which is smaller than the first layer thickness, the connector being attached to the solar cell by means of an adhesively-bonded connection in the second surface region.

Abstract: A solar cell includes a semiconductor wafer, at least one dielectric layer arranged on the semiconductor wafer, a metal layer arranged on the dielectric layer, and a contact structure arranged in the dielectric layer such that the contact structure provides an electrical connection between the metal layer and the semiconductor wafer. The contact structure has at least one first structure having a minimum dimension and at least one second structure having a maximum dimension, wherein the minimum dimension and the maximum dimension are defined along a surface of the semiconductor wafer and the minimum dimension of the first structure is greater than the maximum dimension of the second structure.