Abstract: A method of filling gaps between adjacent gate electrodes of a semiconductor structure. A self-planarizing material is deposited over the structure. A first portion of such material flow between the gate electrode to fill the gaps and a second portion of such material becomes deposited over tops of the gate electrodes and over the gaps to form a layer with a substantially planar surface. A phosphorous dopant is formed in the second portion of the self-planarizing material. Thus, relatively small gaps may be filled effectively with a layer having a very planar surface for subsequent photolithography. The phosphorous dopant provides gettering to remove adverse effects of alkali contaminant ions which may enter the gap filling material. The dielectric constant of the material filing the gaps, i.e., the first portion of the gap filling material, being substantially free of such contaminants, has a relatively low dielectric constant thereby reducing electrical coupling between adjacent electrodes.

Abstract: A method for forming a CMOS device. The method includes forming a gate oxide over a surface of a semiconductor substrate. A first doped layer is formed over the gate oxide. The first doped layer is lithographically patterned comprising selectively removing a portion of such first doped layer to expose a first portion of the gate oxide with the first doped layer remaining disposed over a second laterally positioned portion of the gate oxide. A second doped is deposited over the patterned first doped layer, such second doped layer having a dopant different from, for example a conductivity type opposite to, the dopant of the first doped layer. A portion of the second doped layer is deposited over the exposed first portion of the gate oxide and over the first doped layer to provide a pair of vertically positioned regions. A lower region comprises a portion of the first doped layer and an upper region comprising a portion of the second doped layer.

Abstract: Formation of a gate having a polysilicon and silicide layer thereover with reduced resistance and reduced thickness is provided. The polysilicon layer is annealed to diffuse the dopants out from the surface to reduce the dopant concentration to below the level which causes metal rich interface. Thus, a metal silicide layer can be deposited without an intrinsic poly cap layer or requiring the poly to having a decreased dopant concentration. As such, a thinner gate stack having lower sheet resistance and improved reliability is achieved.

Abstract: A trench capacitor having a substrate with a trench extending therein with a nested, e.g., concentric, conductive regions disposed within the trench. A dielectric material is disposed within the substrate. The dielectric material has portions thereof disposed between the concentric conductive regions to dielectrically electrically separate one of the conductive regions from another one of the conductive regions. The dielectrically separated conductive regions provide a pair of electrodes for the capacitor. Selected ones of the concentric conductive regions are electrically connected to provide one of the electrodes for the capacitor. The substrate has a conductive region therein and one of the concentric conductive regions providing one of the electrodes is electrically connected to the conductive region in the substrate. One of the concentric conductive regions is electrically connected to a conductive region in the substrate through a bottom portion of the trench.

Abstract: A DRAM cell is disposed in an electrically isolated region of a semiconductor body. The cell includes a storage capacitor disposed in a trench. The capacitor is disposed entirely within the isolated region of the semiconductor body. The cell includes a transistor disposed in the isolated region. The transistor has a pair of gates. A word line is provided for addressing the cell. The word line has an electrical contact region to the transistor. The word line contact region is disposed entirely within the isolated region of the semiconductor body. The transistor has an active area. The active area has source, drain, and channel regions. The active area is disposed entirely within the isolated region of the semiconductor body. A bit line is provided for the cell. The bit line is in electrical contact with the gates of the transistor at a pair of bit line contact regions. Both such bit line contact regions are disposed entirely within the isolated region of the cell.

Abstract: A method for the fabrication of a doped silicon layer, includes carrying out deposition by using a process gas containing SiH4, Si2H6 and a doping gas. The doped silicon layer which is thus produced can be used both as a gate electrode of an MOS transistor and as a conductive connection. At a thickness between 50 and 200 nm it has a resistivity less than or equal to 0.5 m&OHgr;cm.

Abstract: Improved trench forming methods for semiconductor substrates using BSG avoid the problems associated with conventional TEOS hard mask techniques. The methods comprise: (a) providing a semiconductor substrate, (b) applying a conformal layer of borosilicate glass (BSG) on the substrate; (c) forming a patterned photoresist layer over the BSG layer whereby a portion of a layer underlying the photoresist layer is exposed, (d) anisotropically etching through the exposed portion of the underlying layer, through any other layers lying between the photoresist layer and the semiconductor substrate, and into the semiconductor substrate, thereby forming a trench in the semiconductor substrate. Preferably, one or more dielectric layers are present on the substrate surface prior to application of the BSG layer. One or more chemical barrier and/or organic antireflective coating layers may be applied over the BSG layer between the BSG layer and the photoresist layer.

Abstract: A reduced metal-rich interface between a poly and metal silicide layer is achieved by insitu doping the metal silicide layer.

Abstract: Improved gap fill of narrow spaces is achieved by using a doped silicate glass having a dopant concentration in a bottom portion thereof which is greater than an amount which causes surface crystal growth and in an upper portion thereof having a lower dopant concentration such that the overall dopant concentration of the doped silicate glass is below that which causes surface crystal growth.

Abstract: An apparatus and method are provided for forming a fluorine doped borophosphosilicate (F-BPSG) glass on a semiconductor device using a low pressure chemical vapor deposition process. The F-BPSG glass exhibits a substantially void-free and particle-free layer on the substrate for structures having gaps as narrow as 0.10 microns and with aspect ratios of 6:1. The reactant gases include sources of boron and phosphorous dopants, oxygen and a mixture of TEOS and FTES. Using a mixture of TEOS and FTES in a low pressure CVD process provides a F-BPSG layer having the above enhanced characteristics. It is a preferred method of the invention to perform the deposition at a temperature of about 750-850.degree. C. and a pressure of 1 to 3 torr to provide for in situ reflow of the F-BPSG during the deposition process. An anneal is also preferred under similar conditions in the same chemical vapor deposition chamber to further planarize the F-BPSG surface.

Abstract: Improved gap fill of narrow spaces is achieved by using a doped silicate glass having a dopant concentration in a bottom portion thereof which is greater than an amount which causes surface crystal growth and in an upper portion thereof having a lower dopant concentration such that the overall dopant concentration of the doped silicate glass is below that which causes surface crystal growth.

Abstract: Capacitor storage charge can be increased by increasing storage node area. A high aspect surface ratio stack capacitor is produced without increasing overall cell dimensions. The node is formed with layers of low doped and high doped concentration borophosphosilicate glass which is deposited by a single process step with precise nanometer dimensions, are selectively etched so that either doped or undoped layers will have a higher etch rate. This etching creates finger-like projections in the node, which provide for greater surface area using a very simplified process requiring fewer processing steps.

Abstract: A method for planarizing a semiconductor structure having a first surface region with a high aspect ratio topography and a second surface region with a low aspect ratio topography. A flowable material is deposited over the first and second surface regions of the structure. A portion of the material fills gaps in the high aspect ratio topography to form a substantially planar surface over the high aspect ratio topography. A doped layer, for example phosphorus doped glass, is formed over the flowable oxide material. The doped layer is disposed over the high aspect ratio and over the low aspect ratio regions. Upper surface portions over the low aspect ratio region are higher than an upper surface of the flowable material. The upper portion of the doped layer is removed over both the first and second surface portions to form a layer with a substantially planar surface above both the high aspect ratio region and the low aspect ratio region.

Abstract: A method for forming a Self Aligned Contact in a semiconductor device includes incorporating carbon into a nitride layer during or following the formation of the nitride layer on a semiconductor substrate.

Abstract: Fabrication of devices that produces a surface with reduced dishing caused by polishing. The reduced dishing is the result of forming a first layer that partially covers a complex surface topography and a second layer the covers the surface topography. The second layer being more resistant to polishing than the first so as to reduce dishing in the wide spaces of the complex topography.

Abstract: A method and apparatus for forming a multi-constituent device layer on a wafer surface are disclosed. The multi-constituent device layer is formed by flowing a first chemistry comprising a first constituent and a second chemistry comprising a second constituent via a segmented delivery system into a reaction chamber. The reaction chamber comprises a susceptor for supporting and rotating the wafers. The segmented delivery system comprises alternating first and second segments into which the first and second chemistries, respectively, are flowed. The first segments comprise an area that is greater than an area of the second segments by an amount sufficient to effectively reduce the diffusion path of the first constituent. Reducing the diffusion path of the first constituent results in a more uniform distribution of the first constituent within the device layer.

Abstract: A method of fabricating a semiconductor structure utilizing doped silicate glass on a substrate of a wafer. The method includes the step forming a modulation doped silicate glass structure over a first layer of the wafer. The modulation doped silicate glass structure is formed by depositing at least two alternating layers of heavily-doped silicate glass and lightly-doped silicate glass over the first layer. Both the heavily-doped silicate glass and lightly-doped silicate glass layers may comprise glass doped with both a first dopant and a second dopant. The first dopant may represent, for example, phosphorous, and the second dopant may represent, for example, boron.

Abstract: Capacitor storage charge can be increased by increasing storage node area. A high aspect surface ratio stack capacitor is produced without increasing overall cell dimensions. The node is formed with layers of low doped and high doped concentration borophosphosilicate glass which is deposited by a single process step with precise nanometer dimensions, are selectively etched so that either doped or undoped layers will have a higher etch rate. This etching creates finger-like projections in the node, which provide for greater surface area using a very simplified process requiring fewer processing steps.