Abstract: A method for operating a microcontroller. The microcontroller includes a plurality of resources, a plurality of virtual machines being executed in the microcontroller, a coordination unit being superordinate to the plurality of virtual machines. Access information concerning accesses of the plurality of virtual machines to the plurality of resources is stored in the coordination unit. In the event that one of the virtual machines requests a reset of one of the resources, the coordination unit checks on the basis of the access information, which of the virtual machines are accessing this resource. The coordination unit determines on the basis of this check, whether the resource will be reset or whether a substitute measure will be taken.

Abstract: A device for operation of a system having a plurality of storage modules and one or a plurality of computing units. The device ascertains, for a first storage module of the plurality of storage modules, an overall access time of a computing unit of the computing unit(s) to this one data element in this first storage module, as a function of a read access frequency, and ascertains the overall access time, also as a function of the duration of a read access of this computing unit to this first storage module. The device decides, as a function of this ascertained overall access time of this computing unit to this data element in this first storage module, whether the data element is stored in this first storage module or in another of the storage module(s).

Abstract: A circuit arrangement for a data processing system is configured to process data in multiple modules. The circuit arrangement is configured to provide a clock as well as a time base and/or a base of at least one further physical quantity for each of the multiple modules. The circuit arrangement also comprises a central routing unit, which is connected to several of the multiple modules. Via the central routing unit, the modules can periodically exchange data based on the time base and/or on the base of the at least one further physical quantity. The several modules are configured to process data independently of and in parallel to other modules of the several modules.

Abstract: A circuit arrangement for a data processing system is configured to process data in multiple modules. The circuit arrangement is configured to provide a clock as well as a time base and/or a base of at least one further physical quantity for each of the multiple modules. The circuit arrangement also comprises a central routing unit, which is connected to several of the multiple modules. Via the central routing unit, the modules can periodically exchange data based on the time base and/or on the base of the at least one further physical quantity. The several modules are configured to process data independently of and in parallel to other modules of the several modules.

Abstract: An emulation system and emulation method for a no longer available microcontroller, having a supplyable microcontroller and emulation software able to be run thereon, and having an interpreter, the emulation software forming a software layer between the hardware of the available microcontroller and an operating software of the no longer available microcontroller, and the software being adapted in such a way that the hardware of the available microcontroller in conjunction with the additional emulation software behaves like the hardware of the no longer available microcontroller, and the interpreter is adapted in order to represent address, code and data information of the operating software of the no longer available microcontroller to functionally equivalent address, code and data information of the available microcontroller.

Abstract: A companion chip for a microcontroller has a microprocessor bus domain and a peripheral module bus domain, which are connected to each other via a bus bridge. The microprocessor bus domain includes at least one microprocessor core, and the peripheral module bus domain includes at least one global time-management module as well as modules for communication with the outside world and for signal processing. The companion chip further includes at least one FIFO module for transmitting data within the chip, and between the chip and the microcontroller, and a management module connected to the FIFO module, which ensures the consistency of the data by associating a respective time value and/or an angle of rotation.

Abstract: A signal acquisition device which receives an input signal, a physical data and a timing data to generate an output data. The signal acquisition device keeps monitoring the input signal for a valid edge. When a valid edge is detected, the signal acquisition device reads the physical data from a physical data processing module and a timing data from a timing module to generate the output data which comprises the new state of the input signal, the physical data and the timing data. The output data is written to a storage arrangement and also sent out to CPU or any other devices.

Abstract: A companion chip for a microcontroller has a microprocessor bus domain and a peripheral module bus domain, which are connected to each other via a bus bridge. The microprocessor bus domain includes at least one microprocessor core, and the peripheral module bus domain includes at least one global time-management module as well as modules for communication with the outside world and for signal processing. The companion chip further includes at least one FIFO module for transmitting data within the chip, and between the chip and the microcontroller, and a management module connected to the FIFO module, which ensures the consistency of the data by associating a respective time value and/or an angle of rotation.

Abstract: The invention relates to a communication method and interface between a companion chip (CC) and a microcontroller (MC), a communication protocol being transmitted, having a first group of data (10) being drawn on for direct, non-real-time-critical access to the chip (CC), and a second group of data (20) based on which a real-time-critical access to the chip (CC) takes place, the data groups (10, 20) each comprising an operation code (OC), the length of which is shorter in the second data group (20) than in the first data group (10), and each data group (10, 20) being identifiable by the bit pattern of the operation code (OC).

Abstract: An emulation system and emulation method for a no longer available microcontroller, having a supplyable microcontroller and emulation software able to be run thereon, and having an interpreter, the emulation software forming a software layer between the hardware of the available microcontroller and an operating software of the no longer available microcontroller, and the software being adapted in such a way that the hardware of the available microcontroller in conjunction with the additional emulation software behaves like the hardware of the no longer available microcontroller, and the interpreter is adapted in order to represent address, code and data information of the operating software of the no longer available microcontroller to functionally equivalent address, code and data information of the available microcontroller.

Abstract: A method of protecting a microcomputer system against manipulation of data stored in a memory arrangement of the microcomputer system, in particular a control program stored there. Checking mechanisms are executed at preselectable points in times to check for manipulation of the data. To permit effective blocking of manipulated data stored in the memory arrangement, new data is stored at least partially in a volatile memory, in particular in a random access memory, in reprogramming or new programming of the memory arrangement, the checking mechanisms are executed and the portion of the new data stored in the volatile memory is copied to the memory arrangement if no manipulation of the new data has been detected.

Abstract: A method for providing dynamic memory management, and a memory device and a system for implementing this method. In addition, a computer program and a computer program product. The memory device includes a first memory block, in which a startup program is stored, and a number of additional memory blocks. The first memory block and the additional memory blocks are connected by a chained list, which is executed at the time of checking of the memory device. The startup program obtains data necessary for a check from the memory blocks themselves.

Abstract: A method of protecting a microcomputer system against manipulation of data stored in a memory arrangement of the microcomputer system, in particular a control program stored there. Checking mechanisms are executed at preselectable points in times to check for manipulation of the data. To permit effective blocking of manipulated data stored in the memory arrangement, new data is stored at least partially in a volatile memory, in particular in a random access memory, in reprogramming or new programming of the memory arrangement, the checking mechanisms are executed and the portion of the new data stored in the volatile memory is copied to the memory arrangement if no manipulation of the new data has been detected.