Abstract: A method of fabricating a self-aligned borderless contact in a semiconductor device. The semiconductor device includes a first conductor level, a patterned conductor level defining a pair of spaced apart conducting segments, and a dielectric insulating layer disposed between the first conductor level and the patterned conductor level, and over the pair of spaced apart conducting segments of the patterned conductor level. The method comprises the steps of etching a contact hole in a selected region of the dielectric insulating layer which lies above and is substantially aligned between the pair of the segments. The etching continues through the dielectric insulating layer so that a portion of the dielectric insulating layer remains between the contact hole and the first conductor level. A spacer is formed which lines the contact hole.

Abstract: A method for globally planarizing an integrated circuit device wafer having a plurality of structures disposed on a surface thereof, the structures forming up and down features on the wafer's surface. The method involves depositing a fill layer over the surface of the wafer to cover the structures. Next, an etch mask layer is deposited over the fill layer. After the etch mask layer is fabricated, openings are formed in the etch mask layer to expose areas of the fill layer that are to be subsequently etched. This is accomplished in the first embodiment of the invention by creating self aligned openings in the etch mask layer using CMP if the gaps between the structures are only partially filled. If the gaps between the structures are completely filled, openings in the etch mask layer can be provided by patterning the etch mask layer using lithography and performing an optional spacer deposition and etching step as described in a second embodiment of the invention.