Abstract: A clock module includes a main precision oscillator generating a first clock signal of a predetermined frequency, a receiving module receiving a time reference and providing a time reference signal controlling the main oscillator, and a detector for detecting a failure of the main oscillator or of the time reference signal. The detector includes: a second oscillator not controlled by the clock module and delivering a second clock signal of predetermined frequency; and a processor configured to measure a first phase difference between the first clock signal and the time reference signal, a second phase difference between the first clock signal and the second clock signal, and a third phase difference between the time reference signal and the second clock signal. The processor is configured to calculate calculating drifts of the first order of the three phase differences measured so as to determine respective variations of the three phase differences.

Abstract: A system, non-transitory computer readable medium, and method include entering redundant oscillators and a cascaded oscillator of a spoofing resistant system into an initialization state. All but one of the redundant oscillators are disciplined to a time-and-frequency external input into normal disciplining state with the remaining one of the redundant oscillators in a holdover state. When all but one of the redundant oscillators have reached the normal disciplining state, placing all but one of the redundant oscillators into the holdover state, disciplining the remaining one of the redundant oscillators to the time and frequency external input, and disciplining the cascaded oscillator to one of the all but one of the redundant oscillators now in the holdover state. When the remaining one of the redundant oscillators and the cascaded oscillator have reached the normal disciplining state, transitioning from an initialization stage to a steady state management stage.

Abstract: A system wherein when a normal state is entered: discipline only one of at least three oscillators to an external reference; output frequency and time based on the other oscillators not being disciplined to the external reference; and monitor the output frequency difference of the one of the oscillators being disciplined and a composite value of the output frequency difference among the other oscillators. A spoofing state is identified when the monitored difference is more than a difference threshold. When the spoofing state is identified: reset the frequency and time of the oscillator in the spoofing state to match the composite value of the other oscillators; resume disciplining the oscillator in the spoofing state from the external reference after expiration of a time period; and clear the spoofing state and return to the normal state when the oscillators have the output frequency differences among the oscillators below the difference threshold.