Abstract: A method for switching power transistors in a power transistor circuit. The power transistors each have a gate, which is driven sequentially by at least three control values in the case of a switch-on sequence and/or a switch-off sequence. A switchover occurs between the control values at specific times. The specific times are determined or modified by a controller, which is driven by a Miller plateau detector for detecting a Miller plateau in a gate-source voltage of the respective power transistor.

Abstract: A transistor device includes a plurality of transistor cells. Each transistor cell includes two load electrodes and a control electrode. The two load electrodes of the transistor cells are arranged spaced apart from each other in a first direction. A first pitch between adjacent load electrodes of a first subset of pairs of the two load electrodes is smaller than a second pitch between adjacent load electrodes of a second subset of pairs of the two load electrodes. Airgaps are provided between adjacent load electrodes of the second subset of pairs.

Abstract: The disclosure relates to a method for switching power transistors in a power transistor circuit. The power transistors each have a gate, which is driven sequentially by at least three control values in the case of a switch-on sequence and/or a switch-off sequence. A switchover occurs between the control values at specific times. The specific times are determined or modified by a controller, which is driven by a Miller plateau detector for detecting a Miller plateau in a gate-source voltage of the respective power transistor.