Abstract: A qubit device or system having isolated bottom corner gates includes a semiconductor substrate and a semiconductor fin perpendicularly adjoining a top surface of the substrate. The qubit device also includes a first gate located at a first corner between a first side of the fin and the top surface of the substrate, and a second gate located at a second corner between a second, opposite side of the fin and the top surface of the substrate. The first and second gates are electrically isolated from each other and used to control a first quantum dot near the top of the fin. A third gate located at the first corner has a contact for accumulating a channel to facilitate charge transport to and from a second quantum dot located near the bottom of the fin accumulated using the first and second gates.

Abstract: A superconductor device includes a substrate. There is a first silicide and a second silicide located on opposite sides of a silicon channel and on top of the substrate. A first superconducting contact is in contact with the first silicide. A second superconducting contact is in contact with the second silicide. A dielectric is located between the first and second superconducting contacts. A gate is on top of the gate dielectric.

Abstract: An electrostatic discharge (ESD) protection circuit is configured to protect a target circuit that operates in a cryogenic temperature is provided. The ESD protection circuit connects a terminal of the target circuit and a ground potential with no connection to a bias potential. When the ESD protection circuit receives a voltage potential at the terminal of the target circuit, the ESD protection circuit (i) disallows electrical current to flow through from the received voltage potential when the device is at a cryogenic temperature and (ii) allows electrical current to flow through from the received voltage potential when the device is at a room temperature.

Abstract: An electrostatic discharge (ESD) protection circuit is configured to protect a target circuit that operates in a cryogenic temperature is provided. The ESD protection circuit connects a terminal of the target circuit and a ground potential with no connection to a bias potential. When the ESD protection circuit receives a voltage potential at the terminal of the target circuit, the ESD protection circuit (i) disallows electrical current to flow through from the received voltage potential when the device is at a cryogenic temperature and (ii) allows electrical current to flow through from the received voltage potential when the device is at a room temperature.

Abstract: A method of modifying a resonant frequency of a quantum device includes generating an ion beam having a beam energy and exposing a surface of the quantum device to the ion beam for an exposure time. The ion beam is incident onto the quantum device at an oblique angle that is less than 90 degrees as measured from the surface of the quantum device. The quantum device includes a Josephson junction, the ion beam exposing the quantum device proximate to the Josephson junction to modify a property of the Josephson junction, the property being associated with the resonant frequency of the quantum device.

Abstract: A method of modifying a resonant frequency of a quantum device includes generating an ion beam having a beam energy and exposing a surface of the quantum device to the ion beam for an exposure time. The ion beam is incident onto the quantum device at an oblique angle that is less than 90 degrees as measured from the surface of the quantum device. The quantum device includes a Josephson junction, the ion beam exposing the quantum device proximate to the Josephson junction to modify a property of the Josephson junction, the property being associated with the resonant frequency of the quantum device.

Abstract: A device package includes a chip carrier having a cavity and one or more microwave waveguides configured to route signals. There is a chip including one or more pads and located within the cavity of the chip carrier. Each pad is aligned with a corresponding connector pad of a microwave waveguide of the one or more microwave waveguides of the chip carrier. At least one of the one or more pads is coupled to the connector pad of the corresponding microwave waveguide by way of an overlap capacitive coupling between the at least one pad and the aligned corresponding connector pad of the microwave waveguide.